📄 timer_set.rpt
字号:
C10 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 18/96 ( 18%)
Total logic cells used: 315/576 ( 54%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.34/4 ( 83%)
Total fan-in: 1054/2304 ( 45%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 18
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 315
Total flipflops required: 52
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 111/ 576 ( 19%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 8 8 8 6 8 8 6 8 8 0 8 8 8 8 8 8 8 8 8 8 8 4 184/0
B: 0 8 0 8 0 0 0 0 0 0 0 1 0 8 8 7 8 8 6 8 8 8 3 6 8 103/0
C: 0 0 8 0 7 8 1 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28/0
Total: 8 16 16 16 15 16 7 8 8 10 8 9 0 16 16 15 16 16 14 16 16 16 11 14 12 315/0
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\timer_set.rpt
timer_set
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 cp
54 - - - -- INPUT 0 0 0 3 key0
124 - - - -- INPUT 0 0 0 1 key1
56 - - - -- INPUT 0 0 0 2 key2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\timer_set.rpt
timer_set
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
99 - - A -- OUTPUT 0 1 0 0 numout0
10 - - A -- OUTPUT 0 1 0 0 numout1
102 - - A -- OUTPUT 0 1 0 0 numout2
97 - - A -- OUTPUT 0 1 0 0 numout3
7 - - A -- OUTPUT 0 1 0 0 segout0
101 - - A -- OUTPUT 0 1 0 0 segout1
11 - - A -- OUTPUT 0 1 0 0 segout2
95 - - A -- OUTPUT 0 1 0 0 segout3
100 - - A -- OUTPUT 0 1 0 0 segout4
98 - - A -- OUTPUT 0 1 0 0 segout5
96 - - A -- OUTPUT 0 1 0 0 segout6
72 - - - 04 OUTPUT 0 0 0 0 segout7
79 - - C -- OUTPUT 0 1 0 0 selout0
83 - - C -- OUTPUT 0 1 0 0 selout1
82 - - C -- OUTPUT 0 1 0 0 selout2
80 - - C -- OUTPUT 0 1 0 0 selout3
81 - - C -- OUTPUT 0 1 0 0 selout4
78 - - C -- OUTPUT 0 1 0 0 selout5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\max+plusii learning\course and others\vhdl\timer_set.rpt
timer_set
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 13 AND2 0 2 0 1 |counter24:u3|LPM_ADD_SUB:78|addcore:adder|:59
- 8 - B 14 AND2 0 3 0 1 |counter24:u3|LPM_ADD_SUB:78|addcore:adder|:63
- 6 - B 14 AND2 0 4 0 1 |counter24:u3|LPM_ADD_SUB:78|addcore:adder|:67
- 2 - B 14 DFFE + 0 3 0 3 |counter24:u3|q4 (|counter24:u3|:13)
- 7 - B 14 DFFE + 0 3 0 4 |counter24:u3|q3 (|counter24:u3|:14)
- 4 - B 14 DFFE + 0 3 0 5 |counter24:u3|q2 (|counter24:u3|:15)
- 3 - B 14 DFFE + 0 3 0 6 |counter24:u3|q1 (|counter24:u3|:16)
- 1 - B 14 DFFE + 0 2 0 8 |counter24:u3|q0 (|counter24:u3|:17)
- 5 - B 14 OR2 ! 1 3 0 5 |counter24:u3|:51
- 1 - B 24 OR2 s 0 3 0 1 |counter24:u3|~216~1
- 7 - B 21 AND2 0 3 0 3 |counter60:u1|LPM_ADD_SUB:83|addcore:adder|:67
- 8 - B 21 AND2 0 2 0 1 |counter60:u1|LPM_ADD_SUB:83|addcore:adder|:71
- 4 - B 21 DFFE + 0 4 0 5 |counter60:u1|q5 (|counter60:u1|:13)
- 3 - B 21 DFFE + 0 4 0 4 |counter60:u1|q4 (|counter60:u1|:14)
- 6 - B 21 DFFE + 0 3 0 5 |counter60:u1|q3 (|counter60:u1|:15)
- 1 - B 21 DFFE + 0 4 0 5 |counter60:u1|q2 (|counter60:u1|:16)
- 5 - B 21 DFFE + 0 3 0 6 |counter60:u1|q1 (|counter60:u1|:17)
- 2 - B 21 DFFE + 0 2 0 6 |counter60:u1|q0 (|counter60:u1|:18)
- 7 - B 16 DFFE + 0 2 0 1 |counter60:u1|dly (|counter60:u1|:19)
- 2 - B 20 OR2 s 0 4 0 1 |counter60:u1|~173~1
- 1 - B 20 OR2 ! 1 3 0 7 |counter60:u1|:180
- 8 - B 17 AND2 0 3 0 1 |counter60:u2|LPM_ADD_SUB:83|addcore:adder|:67
- 7 - B 17 AND2 0 4 0 2 |counter60:u2|LPM_ADD_SUB:83|addcore:adder|:71
- 1 - B 17 DFFE + 0 4 0 6 |counter60:u2|q5 (|counter60:u2|:13)
- 5 - B 17 DFFE + 0 3 0 5 |counter60:u2|q4 (|counter60:u2|:14)
- 3 - B 17 DFFE + 0 3 0 5 |counter60:u2|q3 (|counter60:u2|:15)
- 2 - B 17 DFFE + 0 4 0 5 |counter60:u2|q2 (|counter60:u2|:16)
- 6 - B 17 DFFE + 0 3 0 6 |counter60:u2|q1 (|counter60:u2|:17)
- 3 - B 16 DFFE + 0 2 0 8 |counter60:u2|q0 (|counter60:u2|:18)
- 5 - B 16 DFFE + 0 2 0 1 |counter60:u2|dly (|counter60:u2|:19)
- 4 - B 17 OR2 s 0 4 0 1 |counter60:u2|~173~1
- 4 - B 16 OR2 ! 1 3 0 7 |counter60:u2|:180
- 2 - C 10 AND2 0 3 0 3 |LPM_ADD_SUB:383|addcore:adder|:143
- 2 - C 05 AND2 0 3 0 4 |LPM_ADD_SUB:383|addcore:adder|:151
- 1 - C 05 AND2 0 4 0 4 |LPM_ADD_SUB:383|addcore:adder|:163
- 2 - C 06 AND2 0 4 0 4 |LPM_ADD_SUB:383|addcore:adder|:175
- 6 - C 06 AND2 0 4 0 3 |LPM_ADD_SUB:383|addcore:adder|:187
- 1 - B 02 AND2 0 3 0 4 |LPM_ADD_SUB:383|addcore:adder|:195
- 6 - B 02 AND2 0 4 0 3 |LPM_ADD_SUB:383|addcore:adder|:207
- 2 - B 02 DFFE + 0 3 0 4 q21 (:145)
- 8 - B 02 DFFE + 0 2 0 1 q20 (:146)
- 7 - B 02 DFFE + 0 1 0 2 q19 (:147)
- 5 - B 02 DFFE + 0 3 0 1 q18 (:148)
- 4 - B 02 DFFE + 0 2 0 2 q17 (:149)
- 3 - B 02 DFFE + 0 1 0 3 q16 (:150)
- 6 - C 03 DFFE + 0 2 0 14 q15 (:151)
- 1 - B 12 DFFE + 0 1 0 22 q14 (:152)
- 1 - C 06 DFFE + 0 3 0 8 q13 (:153)
- 8 - C 06 DFFE + 0 2 0 2 q12 (:154)
- 7 - C 06 DFFE + 0 1 0 3 q11 (:155)
- 5 - C 06 DFFE + 0 3 0 1 q10 (:156)
- 4 - C 06 DFFE + 0 2 0 2 q9 (:157)
- 3 - C 06 DFFE + 0 1 0 3 q8 (:158)
- 7 - C 05 DFFE + 0 3 0 1 q7 (:159)
- 6 - C 05 DFFE + 0 2 0 2 q6 (:160)
- 5 - C 05 DFFE + 0 1 0 3 q5 (:161)
- 4 - C 05 DFFE + 0 2 0 1 q4 (:162)
- 3 - C 05 DFFE + 0 1 0 2 q3 (:163)
- 4 - C 10 DFFE + 0 2 0 1 q2 (:164)
- 1 - C 10 DFFE + 0 1 0 2 q1 (:165)
- 3 - C 10 DFFE + 0 0 0 3 q0 (:166)
- 4 - B 18 DFFE + 0 1 0 2 dly (:167)
- 4 - B 04 DFFE + 0 1 0 6 sdly (:168)
- 2 - B 04 DFFE + 1 2 0 3 d0 (:187)
- 3 - B 04 DFFE + 0 3 0 2 d1 (:188)
- 6 - B 04 DFFE + 0 3 0 1 s~194 (:189)
- 8 - B 04 DFFE + 0 3 0 1 r (:190)
- 4 - B 15 DFFE + 0 1 0 2 d0~208 (:194)
- 5 - B 15 DFFE + 0 1 0 1 d1~210 (:195)
- 7 - B 15 DFFE + 0 4 0 1 q2~220 (:198)
- 2 - B 15 DFFE + ! 0 3 0 9 q1~220 (:199)
- 1 - B 15 DFFE + ! 0 2 0 10 q0~220 (:200)
- 5 - B 04 AND2 0 4 0 1 :690
- 7 - B 04 AND2 0 4 0 1 :696
- 1 - A 11 OR2 0 4 1 0 :854
- 2 - A 11 OR2 0 4 1 0 :888
- 8 - A 10 OR2 0 4 1 0 :922
- 8 - A 11 OR2 0 4 1 0 :956
- 3 - A 11 OR2 0 4 1 0 :990
- 5 - A 11 OR2 0 4 1 0 :1024
- 6 - B 18 OR2 s 0 4 0 1 ~1057~1
- 3 - B 18 OR2 0 2 0 7 :1057
- 1 - A 10 OR2 s ! 0 2 0 2 ~1058~1
- 6 - A 10 OR2 0 4 1 0 :1058
- 2 - B 18 OR2 s ! 1 2 0 3 ~1108~1
- 5 - B 18 OR2 ! 0 4 0 1 :1109
- 1 - B 18 OR2 ! 0 4 0 6 :1115
- 8 - B 16 OR2 ! 0 4 0 1 :1116
- 2 - B 16 OR2 ! 0 4 0 6 :1122
- 6 - B 16 OR2 ! 0 4 0 1 :1123
- 1 - B 16 OR2 ! 0 4 0 5 :1130
- 5 - C 03 AND2 0 3 1 0 :1212
- 1 - C 03 AND2 0 3 1 0 :1216
- 2 - C 03 AND2 0 3 1 0 :1220
- 4 - C 03 AND2 0 3 1 0 :1224
- 3 - C 03 AND2 0 3 1 0 :1228
- 7 - C 03 AND2 0 3 1 0 :1277
- 6 - B 24 OR2 s 0 2 0 10 ~1391~1
- 3 - B 24 OR2 s 0 2 0 8 ~1400~1
- 2 - B 24 OR2 ! 0 2 0 9 :1433
- 3 - B 22 OR2 ! 0 4 0 36 :1562
- 7 - B 24 OR2 ! 0 4 0 1 :1571
- 5 - B 24 OR2 ! 0 3 0 21 :1574
- 2 - B 22 OR2 0 4 0 1 :1583
- 1 - B 22 OR2 0 3 0 17 :1586
- 3 - B 23 OR2 ! 0 2 0 1 :1597
- 2 - B 23 OR2 s 0 2 0 1 ~1598~1
- 1 - B 23 OR2 ! 0 4 0 8 :1598
- 4 - B 24 OR2 ! 0 4 0 1 :1607
- 8 - B 24 OR2 ! 0 3 0 39 :1610
- 6 - B 13 OR2 ! 0 2 0 1 :1621
- 5 - B 19 OR2 s 0 3 0 1 ~1622~1
- 4 - B 19 OR2 ! 0 3 0 8 :1622
- 3 - A 19 AND2 0 4 0 3 :1685
- 5 - A 19 AND2 0 2 0 2 :1692
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -