usb_new_rgen_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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---- File >>> usb_new_rgen_ent.vhdl 
---- Iden >>>							951124-17:35:58
----
---- Project:		USB Development
---- Customer:		Philips_ITCL
----
---- Module:		entity RGEN
---- Written by:	Jan Decaluwe (e-mail: [e-mail])
----			Easics nv
----			Kapeldreef 60
----			B-3001	Leuven
----			Belgium
----			Tel [phone]
----			Fax [phone]
----			e-mail: [e-mail]
----
---- Creation Date:	Fri, 24 Nov 1995
----
---- Purpose:
----
---- Revision history:
----
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_CONFIGURATION.all;

entity RGEN is
  port  (
          --- generated reset signals  ---
	  USB_Reset_O_N:     out one_bit; -- to controller
	  RG_SetSE0Int:      out boolean; -- sets SE0 interrupt
          RG_BUSReset:       out boolean; -- Bus Reset
	  Reset_N:           out one_bit; -- reset active low
	  PUReset_N:         out one_bit; -- power up reset
	  Reset12MHzRef_N:   out one_bit; -- referential clock
	  Reset48MHz_N:      out one_bit; -- 48 MHz reset

          --- inputs ---
	  UP_DsLineBits:     in  two_bits; -- downstream USB bus
	  PU_Reset_N:        in  one_bit; -- power up reset

          --- system ---
	  FsClk:             in  one_bit; -- clock
	  Clk12MHzRef:       in  one_bit; -- 12 MHz reference clock
	  Clk48MHz:          in  one_bit; -- 48 MHz clock
	  ConfigArray:       in  S_ConfigArray; -- Configuration info
	  RG_BusActive:      out boolean; -- Bus is not idle
	  TestMode:          in  one_bit -- test control pin
	);
end RGEN;