usb_new_usbpvci_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usbpvci_str.vhdl 
--
--  Module          : USBPVCI 
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     :The architecture of USBPVCI block. This module includes
--                   the following sub-modules:
--                   GLUE,
--                   TX_SF_DPDM,
--                   USB_INT. 
--
--  Status          : 
--
--  Contact address : 
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;
use work.PCK_HANDLERS.all;
use work.PCK_USB.all;

library work;
use work.PCK_APB.all;

library work;
use work.all;

library work;
use work.all;

architecture STR of USBPVCI is

  component GLUE
   port(
        -- Interface to APB WRAPPER

        r_data:                     out std_logic_vector(31 downto 0);
        gnt:                        out std_logic;
        clk:                        in  std_logic;
        pvci_reset_n:               in  std_logic;
        req:                        in  std_logic;
        address:                    in  std_logic_vector(7 downto 0);
        rnw:                        in  std_logic;
        w_data:                     in  std_logic_vector(31 downto 0);

	-- Interface to USB_INT

        USB_r_data:                 in  four_bytes;
        USB_gnt:                    in  one_bit;
        USB_clk:                    out one_bit;
        USB_reset_n:                out one_bit;
        USB_req:                    out one_bit;  
        USB_address:                out byte;
        USB_rnw:                    out one_bit;  
        USB_w_data:                 out four_bytes; 
        USB_Int_Req_Irq:            out std_logic;
        USB_Int_Req_Fiq:            out std_logic;
	pvci_reset_n_out:           out std_logic;
	USB_AsynReset_N:            in  std_logic;
        
        -- Clocks 

        Clk12MHzRef:                out one_bit;
        Clk12MHzRef_O:              in  one_bit;
        Clk12MHz_O:                 in  one_bit;
        Clk48MHz:                   out one_bit;
        USB_NeedClk:                out std_logic;
    
        DH_Connect:                 in  boolean;
        FsClk:                      out one_bit;
        HB_UsbLineBits:             out two_bits;  
        HB_UsbDifBit:               out one_bit;  
        HC_ResetDevice:             out booleans(N_EMBEDDED_PORTS -1 downto 0);  
        USB_BitClk:                 in  std_logic;   -- Recovered bit clock
        USB_BitClk_Out:             out std_logic;   -- Recovered bit clock
        USB_MainClk:                in  std_logic;   -- Main clock
    
        -- Connect

        USB_Connect_N:              out std_logic;        -- Controls switch for softconnect
        USB_VBus:                   in  std_logic;        -- Bus power is present
    
        -- Misc 

        ChipID:                     out S_ChipID;         -- Chip ID
        PINConfigArray:             out S_PINConfigArray; -- Pin controllable part of ConfigArray
        Suspend_In:                 out boolean;          -- not(Wake up)
        TestMode:                   out one_bit;          -- Select test mode
        USB_Reset_O_N:              in  one_bit;          -- Bus reset
        USB_Suspended:              in  one_bit;          -- Suspend
        USB_TestMode:               in  std_logic;        -- Select test mode
        VBusAvailable:              out boolean;          -- Bus power is present
   
        -- Open

        CR_DebugRecDataN:           in  one_bit;          -- Open
        CR_DebugRecDataP:           in  one_bit;          -- Open
        Reset12MHzRef_N:            in  one_bit;          -- Open
        SIE_RxUsbLogValue:          in  T_UsbLog_enum;    -- Open
        TM_ClockRestarted:          in  boolean;          -- Open
        TM_Idle5ms:                 in  boolean;          -- Open

        --  Used

        TM_ClockOn:                 in  one_bit;
        
        -- Interface to RAM

        RxRAM_E_N:                  in  one_bit;
        RxRAM_W_N:                  in  one_bit;
        RxRAM_G_N:                  in  one_bit;
        RxRAM_A:                    in  RxRAMAddr_bits;
        RxRAM_DQ_In:                out four_bytes;
        RxRAM_DQ_Out:               in  four_bytes;
      
        TxRAM_E_N:                  in  one_bit;
        TxRAM_W_N:                  in  one_bit;
        TxRAM_G_N:                  in  one_bit;
        TxRAM_A:                    in  TxRAMAddr_bits;
        TxRAM_DQ_In:                out four_bytes;
        TxRAM_DQ_Out:               in  four_bytes;
       
        USB_RxRAM_E_N:              out std_logic;
        USB_RxRAM_W_N:              out std_logic;
        USB_RxRAM_G_N:              out std_logic;
        USB_RxRAM_A:                out std_logic_vector(RxRAMAddr_Width-1 downto 0);
        USB_RxRAM_DQ_In:            in  std_logic_vector(31 downto 0);
        USB_RxRAM_DQ_Out:           out std_logic_vector(31 downto 0);
     
        USB_TxRAM_E_N:              out std_logic;
        USB_TxRAM_W_N:              out std_logic;
        USB_TxRAM_G_N:              out std_logic;
        USB_TxRAM_A:                out std_logic_vector(TxRAMAddr_Width-1 downto 0);
        USB_TxRAM_DQ_In:            in  std_logic_vector(31 downto 0);
        USB_TxRAM_DQ_Out:           out std_logic_vector(31 downto 0);
    
        -- Suspend

        USB_Suspend:                out std_logic;        -- Suspend
    
        SIE_UsbEnable_N:            in  one_bit;  
        TM_EOF2:                    in  boolean;  
        RemoteWakeup:               out boolean;  
        SIE_LowSpeedTransaction:    in  boolean;  
        RG_BUSReset:                in  boolean;  
        TM_IsoToggle:               in  integer range 0 to 1;  
    
        ---------- Upstream port ---------

        Configured_LED:             in  one_bit;                 -- LED
        UP_DM:                      in  one_bit;                 -- Tx D-
        UP_DP:                      in  one_bit;                 -- Tx D+
        UP_DsLineBits:              out two_bits;                -- Rx Bus (D+,D-)
        USB_FrameClock:             in  one_bit;  
        USB_UP_LED_N:               out std_logic;               -- LED
        USB_UP_RxDM:                in  std_logic;               -- Rx D-
        USB_UP_RxDP:                in  std_logic;               -- Rx D+
        USB_UP_RxRCV:               in  std_logic;               -- Rx RCV
        USB_UP_TxDM:                out std_logic;               -- Tx D-
        USB_UP_TxDP:                out std_logic;               -- Tx D+
        USB_UP_TxEnable_N:          out std_logic;               -- Tx Enable
	
	-- Interupt Request signals

        Intr_Request_Irq:           in  one_bit;
        Intr_Request_Fiq:           in  one_bit
        );
  end component;

  component TX_SF_DPDM
   port(
        SIE_TxLogValue:             in  T_UsbLog_enum;
        UP_DP:                      out one_bit;
        UP_DM:                      out one_bit;
        ConfigArray:                in  S_ConfigArray
       );
   end component;

   component USB_INT
    port(

         -- APB interface
         clk:                       in  one_bit;                -- PVCI clock
         pvci_reset_n:              in  one_bit;                -- Reset
         req:                       in  one_bit;                -- Request
         address:                   in  byte;                   -- Address
         rnw:                       in  one_bit;                -- '0' write, '1' read
         w_data:                    in  four_bytes;             -- Write data
         gnt:                       out one_bit;                -- Grant
         r_data:                    out four_bytes;             -- Read data
         error:                     out one_bit;                -- Error
      
         -- Interrupt signals
         Intr_Request_Irq:          out one_bit;                -- IRQ interrupt request
         Intr_Request_Fiq:          out one_bit;                -- FIQ interrupt request

         Clk12MHzRef_O:             out one_bit;
         Clk12MHz_O:                out one_bit;

         ChipID:                    in  S_ChipID;
         ConfigArray:               out S_ConfigArray;
         PINConfigArray:            in  S_PINConfigArray;

         RxRAM_E_N:                 out one_bit;
         RxRAM_W_N:                 out one_bit;
         RxRAM_G_N:                 out one_bit;
         RxRAM_A:                   out RxRAMAddr_bits;
         RxRAM_DQ_In:               in  four_bytes;
         RxRAM_DQ_Out:              out four_bytes;

         TxRAM_E_N:                 out one_bit;
         TxRAM_W_N:                 out one_bit;
         TxRAM_G_N:                 out one_bit;
         TxRAM_A:                   out TxRAMAddr_bits;
         TxRAM_DQ_In:               in  four_bytes;
         TxRAM_DQ_Out:              out four_bytes;

         SIE_LowSpeedTransaction:   out boolean;
         SIE_RxUsbLogValue:         out T_UsbLog_enum;

         -- DH_Interrupt:           out boolean;

         CR_DebugRecDataN:          out one_bit;
         CR_DebugRecDataP:          out one_bit;

         TM_EOF2:                   out boolean;

         RG_BUSReset:               out boolean;
         Reset12MHzRef_N:           out one_bit;
         USB_Reset_O_N:             out one_bit;

         HB_UsbDifBit:              in  one_bit;
         HB_UsbLineBits:            in  two_bits;

         PU_Reset_N:                in  one_bit;
         UP_DsLineBits:             in  two_bits;

         Configured_LED:            out one_bit;

         -- MP_D_Enable_N:          out one_bit;

         HC_ResetDevice:            in  booleans(N_EMBEDDED_PORTS -1 downto 0);

         DH_Connect:                out boolean;
         VBusAvailable:             in  boolean;

         EX_NeedClock:              in  boolean;
         RemoteWakeup:              in  boolean;
         Suspend_In:                in  boolean;
         TM_ClockOn:                out one_bit;
         TM_ClockRestarted:         out boolean;
         TM_Idle5ms:                out boolean;

         USB_Suspended:             out one_bit;

         Clk12MHzRef:               in  one_bit;
         Clk48MHz:                  in  one_bit;

         FsClk:                     in  one_bit;
         TM_IsoToggle:              out integer range 0 to 1;

         TestMode:                  in  one_bit;
         USB_FrameClock:            out one_bit;
         SIE_TxLogValue:            out T_UsbLog_enum;
         SIE_UsbEnable_N:           out one_bit
        );
  end component;

signal  CR_DebugRecDataN:        one_bit;
signal  CR_DebugRecDataP:        one_bit;
signal  ChipID:                  S_ChipID;
signal  Clk12MHzRef:             one_bit;
signal  Clk12MHzRef_O:           one_bit;
signal  Clk12MHz_O:              one_bit;
signal  Clk48MHz:                one_bit;
signal  ConfigArray:             S_ConfigArray;