clockmake.vhd

来自「用max+plusII编写的vhdl程序 乒乓球游戏机」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clockmake IS                                    
    PORT (CLK		: IN STD_LOGIC; 
          CLK_DSP	:OUT   STD_LOGIC; 
          CLK_1HZ 	:OUT STD_LOGIC
          );
 END;
ARCHITECTURE behave OF clockmake IS
SIGNAL    q  : std_logic_vector(21 downto 0);
BEGIN
P0: process(clk)
    begin
      if clk'event and clk='1' then
         q<=q+1;
      end if;
    end process P0;
CLK_1HZ <= q(21);
CLK_DSP <= q(13);
END behave;