📄 datacontrol.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY datacontrol IS
PORT(clk_1hz:IN STD_LOGIC;
clr:IN STD_LOGIC;
tclr:IN STD_LOGIC;
playrloss:IN STD_LOGIC;
playlloss:IN STD_LOGIC;
data:OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END datacontrol;
ARCHITECTURE behave OF datacontrol IS
SIGNAL lscore0,rscore0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL lscore10,rscore10:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ltotal,rtotal:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk_1hz,clr,tclr,playrloss,playlloss)
BEGIN
IF(tclr='0')THEN
rtotal<="0000";
ltotal<="0000";
ELSIF(clr='0')THEN
rscore0<="0000";
lscore0<="0000";
rscore10<="0000";
lscore10<="0000";
ELSIF(clk_1hz'EVENT AND clk_1hz='1')THEN
IF(playlloss='1')THEN
IF(rscore0<9)THEN
rscore0<=rscore0+1;
ELSE
rscore0<="0000";
rscore10<="0001";
END IF;
IF(rscore0="0000" AND rscore10="0001")THEN
rscore0<="0000";
rscore10<="0000";
rtotal<=rtotal+1;
END IF;
END IF;
IF(playrloss='1')THEN
IF(lscore0<9)THEN
lscore0<=lscore0+1;
ELSE
lscore0<="0000";
lscore10<="0001";
END IF;
IF(lscore0="0000" AND lscore10="0001")THEN
lscore0<="0000";
lscore10<="0000";
ltotal<=ltotal+1;
END IF;
END IF;
END IF;
END PROCESS;
data(23 DOWNTO 20)<=ltotal;
data(19 DOWNTO 16)<=lscore10;
data(15 DOWNTO 12)<=lscore0;
data(11 DOWNTO 8)<=rscore10;
data(7 DOWNTO 4)<=rscore0;
data(3 DOWNTO 0)<=rtotal;
END behave;
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