📄 wgetinstr.ant
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-- F:\CPU
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:48:26 2005
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY wGetInstr IS
END wGetInstr;
ARCHITECTURE testbench_arch OF wGetInstr IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\cpu\wGetInstr.ano";
COMPONENT getinstr
PORT (
clr : In std_logic;
rz : In std_logic;
ex : In std_logic;
t : In std_logic_vector (2 DOWNTO 0);
r7 : In std_logic_vector (7 DOWNTO 0);
mar : Out std_logic_vector (15 DOWNTO 0);
mdr : InOut std_logic_vector (15 DOWNTO 0);
rd : Out std_logic;
wr : Out std_logic;
opcode : InOut std_logic_vector (3 DOWNTO 0);
r1 : Out std_logic_vector (2 DOWNTO 0);
r2 : Out std_logic_vector (2 DOWNTO 0);
imm : Buffer std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
SIGNAL clr : std_logic;
SIGNAL rz : std_logic;
SIGNAL ex : std_logic;
SIGNAL t : std_logic_vector (2 DOWNTO 0);
SIGNAL r7 : std_logic_vector (7 DOWNTO 0);
SIGNAL mar : std_logic_vector (15 DOWNTO 0);
SIGNAL mdr : std_logic_vector (15 DOWNTO 0);
SIGNAL rd : std_logic;
SIGNAL wr : std_logic;
SIGNAL opcode : std_logic_vector (3 DOWNTO 0);
SIGNAL r1 : std_logic_vector (2 DOWNTO 0);
SIGNAL r2 : std_logic_vector (2 DOWNTO 0);
SIGNAL imm : std_logic_vector (7 DOWNTO 0);
BEGIN
UUT : getinstr
PORT MAP (
clr => clr,
rz => rz,
ex => ex,
t => t,
r7 => r7,
mar => mar,
mdr => mdr,
rd => rd,
wr => wr,
opcode => opcode,
r1 => r1,
r2 => r2,
imm => imm
);
PROCESS -- Annotate outputs process
VARIABLE TX_TIME : INTEGER :=0;
PROCEDURE ANNOTATE_mar(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",mar,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mar);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_rd(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",rd,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rd);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_wr(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",wr,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wr);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_r1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",r1,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_r2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",r2,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_imm(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",imm,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, imm);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_mdr(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",mdr,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_opcode(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",opcode,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, opcode);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
CHECK_LOOP : LOOP
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
ANNOTATE_mar(TX_TIME);
ANNOTATE_rd(TX_TIME);
ANNOTATE_wr(TX_TIME);
ANNOTATE_r1(TX_TIME);
ANNOTATE_r2(TX_TIME);
ANNOTATE_imm(TX_TIME);
ANNOTATE_mdr(TX_TIME);
ANNOTATE_opcode(TX_TIME);
WAIT FOR 50 ns;
TX_TIME := TX_TIME + 50;
END LOOP CHECK_LOOP;
END PROCESS;
PROCESS
VARIABLE TX_OUT : LINE;
BEGIN
-- --------------------
clr <= transport '1';
rz <= transport '0';
ex <= transport '0';
t <= transport std_logic_vector'("100"); --4
r7 <= transport std_logic_vector'("00000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
t <= transport std_logic_vector'("001"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
ex <= transport '1';
t <= transport std_logic_vector'("100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=500 ns
ex <= transport '0';
t <= transport std_logic_vector'("100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=700 ns
t <= transport std_logic_vector'("001"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
ex <= transport '1';
t <= transport std_logic_vector'("100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=900 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=1000 ns
ex <= transport '0';
t <= transport std_logic_vector'("100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=1100 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=1200 ns
t <= transport std_logic_vector'("001"); --1
-- --------------------
WAIT FOR 100 ns; -- Time=1300 ns
ex <= transport '1';
t <= transport std_logic_vector'("100"); --4
-- --------------------
WAIT FOR 100 ns; -- Time=1400 ns
t <= transport std_logic_vector'("010"); --2
-- --------------------
WAIT FOR 100 ns; -- Time=1500 ns
ex <= transport '0';
-- --------------------
WAIT FOR 200 ns; -- Time=1700 ns
-- --------------------
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
CONFIGURATION getinstr_cfg OF wGetInstr IS
FOR testbench_arch
END FOR;
END getinstr_cfg;
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