wmemcontrol.ant

用VHDL 编写的一个16位的cpu 设计方案

-- F:\CPU
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 03 18:16:22 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wmemcontrol IS
END wmemcontrol;

ARCHITECTURE testbench_arch OF wmemcontrol IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\cpu\wmemcontrol.ano";
	COMPONENT memcontrol
		PORT (
			t : In  std_logic_vector (2 DOWNTO 0);
			rd1 : In  std_logic;
			wr1 : In  std_logic;
			rd2 : In  std_logic;
			wr2 : In  std_logic;
			ex : In  std_logic;
			mdr0out : Out  std_logic_vector (15 DOWNTO 0);
			mdr1out : Out  std_logic_vector (15 DOWNTO 0);
			ABUS : Out  std_logic_vector (15 DOWNTO 0);
			s0 : Out  std_logic_vector (15 DOWNTO 0);
			s2 : Out  std_logic_vector (15 DOWNTO 0);
			mdr0in : In  std_logic_vector (15 DOWNTO 0);
			mdr1in : In  std_logic_vector (15 DOWNTO 0);
			mar0in : In  std_logic_vector (15 DOWNTO 0);
			mar1in : In  std_logic_vector (15 DOWNTO 0);
			DBUS : InOut  std_logic_vector (15 DOWNTO 0);
			nMREQ : Out  std_logic;
			nRD : Out  std_logic;
			nWR : Out  std_logic;
			nBHE : Out  std_logic;
			nBLE : Out  std_logic
		);
	END COMPONENT;

	SIGNAL t : std_logic_vector (2 DOWNTO 0);
	SIGNAL rd1 : std_logic;
	SIGNAL wr1 : std_logic;
	SIGNAL rd2 : std_logic;
	SIGNAL wr2 : std_logic;
	SIGNAL ex : std_logic;
	SIGNAL mdr0out : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr1out : std_logic_vector (15 DOWNTO 0);
	SIGNAL ABUS : std_logic_vector (15 DOWNTO 0);
	SIGNAL s0 : std_logic_vector (15 DOWNTO 0);
	SIGNAL s2 : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr0in : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr1in : std_logic_vector (15 DOWNTO 0);
	SIGNAL mar0in : std_logic_vector (15 DOWNTO 0);
	SIGNAL mar1in : std_logic_vector (15 DOWNTO 0);
	SIGNAL DBUS : std_logic_vector (15 DOWNTO 0);
	SIGNAL nMREQ : std_logic;
	SIGNAL nRD : std_logic;
	SIGNAL nWR : std_logic;
	SIGNAL nBHE : std_logic;
	SIGNAL nBLE : std_logic;

BEGIN
	UUT : memcontrol
	PORT MAP (
		t => t,
		rd1 => rd1,
		wr1 => wr1,
		rd2 => rd2,
		wr2 => wr2,
		ex => ex,
		mdr0out => mdr0out,
		mdr1out => mdr1out,
		ABUS => ABUS,
		s0 => s0,
		s2 => s2,
		mdr0in => mdr0in,
		mdr1in => mdr1in,
		mar0in => mar0in,
		mar1in => mar1in,
		DBUS => DBUS,
		nMREQ => nMREQ,
		nRD => nRD,
		nWR => nWR,
		nBHE => nBHE,
		nBLE => nBLE
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_nMREQ(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nMREQ,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMREQ);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nRD(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nRD,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nRD);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nWR(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nWR,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nWR);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nBHE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nBHE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBHE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nBLE(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nBLE,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBLE);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_mdr0out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",mdr0out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr0out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_mdr1out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",mdr1out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr1out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ABUS(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ABUS,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ABUS);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_s0(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",s0,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s0);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_s2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",s2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DBUS(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DBUS,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DBUS);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_nMREQ(TX_TIME);
		ANNOTATE_nRD(TX_TIME);
		ANNOTATE_nWR(TX_TIME);
		ANNOTATE_nBHE(TX_TIME);
		ANNOTATE_nBLE(TX_TIME);
		ANNOTATE_mdr0out(TX_TIME);
		ANNOTATE_mdr1out(TX_TIME);
		ANNOTATE_ABUS(TX_TIME);
		ANNOTATE_s0(TX_TIME);
		ANNOTATE_s2(TX_TIME);
		ANNOTATE_DBUS(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		wr2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001011"); --B
		rd2 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001011"); --B
		rd2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001100"); --C
		wr2 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001100"); --C
		wr2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001101"); --D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001101"); --D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001110"); --E
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001110"); --E
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		ex <= transport '0';
		-- --------------------
		WAIT FOR 650 ns; -- Time=2650 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION memcontrol_cfg OF wmemcontrol IS
	FOR testbench_arch
	END FOR;
END memcontrol_cfg;