getinstr.twr

用VHDL 编写的一个16位的cpu 设计方案

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Release 6.1i Trace G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml getinstr getinstr.ncd -o
getinstr.twr getinstr.pcf


Design file:              getinstr.ncd
Physical constraint file: getinstr.pcf
Device,speed:             xcv200,-4 (FINAL 1.123 2003-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
clr         |   12.628(R)|   -2.649(R)|clk_BUFGP         |   0.000|
ex          |   11.335(R)|   -0.582(R)|clk_BUFGP         |   0.000|
mdrin<10>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<11>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<12>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<13>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<14>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<15>   |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<1>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<2>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<3>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<4>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<5>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<6>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<7>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<8>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
mdrin<9>    |    3.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
r7<0>       |    3.137(R)|   -0.226(R)|clk_BUFGP         |   0.000|
r7<1>       |    3.536(R)|   -0.466(R)|clk_BUFGP         |   0.000|
r7<2>       |    3.359(R)|   -0.359(R)|clk_BUFGP         |   0.000|
r7<3>       |    3.185(R)|   -0.255(R)|clk_BUFGP         |   0.000|
r7<4>       |    3.306(R)|   -0.305(R)|clk_BUFGP         |   0.000|
r7<5>       |    3.379(R)|   -0.349(R)|clk_BUFGP         |   0.000|
r7<6>       |    3.412(R)|   -0.394(R)|clk_BUFGP         |   0.000|
r7<7>       |    3.792(R)|   -0.622(R)|clk_BUFGP         |   0.000|
rz          |    7.964(R)|   -1.167(R)|clk_BUFGP         |   0.000|
t<0>        |   13.008(R)|   -1.700(R)|clk_BUFGP         |   0.000|
t<1>        |   13.332(R)|   -1.810(R)|clk_BUFGP         |   0.000|
t<2>        |   12.699(R)|   -1.590(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
imm<0>      |   10.713(R)|clk_BUFGP         |   0.000|
imm<1>      |   12.605(R)|clk_BUFGP         |   0.000|
imm<2>      |   11.857(R)|clk_BUFGP         |   0.000|
imm<3>      |   12.239(R)|clk_BUFGP         |   0.000|
imm<4>      |   13.631(R)|clk_BUFGP         |   0.000|
imm<5>      |   12.768(R)|clk_BUFGP         |   0.000|
imm<6>      |   13.998(R)|clk_BUFGP         |   0.000|
imm<7>      |   12.322(R)|clk_BUFGP         |   0.000|
mar<0>      |    7.988(R)|clk_BUFGP         |   0.000|
mar<10>     |    7.911(R)|clk_BUFGP         |   0.000|
mar<11>     |    7.980(R)|clk_BUFGP         |   0.000|
mar<12>     |    7.982(R)|clk_BUFGP         |   0.000|
mar<13>     |    7.982(R)|clk_BUFGP         |   0.000|
mar<14>     |    7.982(R)|clk_BUFGP         |   0.000|
mar<15>     |    7.980(R)|clk_BUFGP         |   0.000|
mar<1>      |    7.988(R)|clk_BUFGP         |   0.000|
mar<2>      |    7.980(R)|clk_BUFGP         |   0.000|
mar<3>      |    7.980(R)|clk_BUFGP         |   0.000|
mar<4>      |    7.975(R)|clk_BUFGP         |   0.000|
mar<5>      |    7.980(R)|clk_BUFGP         |   0.000|
mar<6>      |    7.968(R)|clk_BUFGP         |   0.000|
mar<7>      |    7.911(R)|clk_BUFGP         |   0.000|
mar<8>      |    7.912(R)|clk_BUFGP         |   0.000|
mar<9>      |    7.912(R)|clk_BUFGP         |   0.000|
opcode<0>   |    7.982(R)|clk_BUFGP         |   0.000|
opcode<1>   |    7.968(R)|clk_BUFGP         |   0.000|
opcode<2>   |    7.912(R)|clk_BUFGP         |   0.000|
opcode<3>   |    7.982(R)|clk_BUFGP         |   0.000|
r1<0>       |    7.911(R)|clk_BUFGP         |   0.000|
r1<1>       |    7.944(R)|clk_BUFGP         |   0.000|
r1<2>       |    7.980(R)|clk_BUFGP         |   0.000|
r2<0>       |   14.314(R)|clk_BUFGP         |   0.000|
r2<1>       |   13.827(R)|clk_BUFGP         |   0.000|
r2<2>       |   13.259(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   10.577|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
clr            |mar<0>         |   10.489|
clr            |mar<10>        |    8.787|
clr            |mar<11>        |   10.738|
clr            |mar<12>        |   10.268|
clr            |mar<13>        |   10.268|
clr            |mar<14>        |   11.046|
clr            |mar<15>        |   11.057|
clr            |mar<1>         |   10.489|
clr            |mar<2>         |   11.057|
clr            |mar<3>         |   10.475|
clr            |mar<4>         |   10.728|
clr            |mar<5>         |   10.738|
clr            |mar<6>         |    9.043|
clr            |mar<7>         |    8.787|
clr            |mar<8>         |    8.832|
clr            |mar<9>         |    8.832|
---------------+---------------+---------+

Analysis completed Thu Nov 03 16:39:27 2005
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Peak Memory Usage: 47 MB