walu.vhw

用VHDL 编写的一个16位的cpu 设计方案

-- F:\CPU
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:05:25 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY walu IS
END walu;

ARCHITECTURE testbench_arch OF walu IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT alu
		PORT (
			input1 : In  std_logic_vector (7 DOWNTO 0);
			input2 : In  std_logic_vector (7 DOWNTO 0);
			opreg : In  std_logic_vector (3 DOWNTO 0);
			output : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL input1 : std_logic_vector (7 DOWNTO 0);
	SIGNAL input2 : std_logic_vector (7 DOWNTO 0);
	SIGNAL opreg : std_logic_vector (3 DOWNTO 0);
	SIGNAL output : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : alu
	PORT MAP (
		input1 => input1,
		input2 => input2,
		opreg => opreg,
		output => output
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_output(
			next_output : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (output /= next_output) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns output="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, output);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_output);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0111"); --7
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		input1 <= transport std_logic_vector'("00000101"); --5
		input2 <= transport std_logic_vector'("00001010"); --A
		opreg <= transport std_logic_vector'("0111"); --7
		-- --------------------
		WAIT FOR 2100 ns; -- Time=2900 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION alu_cfg OF walu IS
	FOR testbench_arch
	END FOR;
END alu_cfg;