📄 wexe.vhw

📁 用VHDL 编写的一个16位的cpu 设计方案
💻 VHW
字号:
-- F:\CPU
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:31:12 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wexe IS
END wexe;

ARCHITECTURE testbench_arch OF wexe IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT exe
		PORT (
			ex : In  std_logic;
			opcode : In  std_logic_vector (3 DOWNTO 0);
			r1 : In  std_logic_vector (2 DOWNTO 0);
			r2 : In  std_logic_vector (2 DOWNTO 0);
			t : In  std_logic_vector (2 DOWNTO 0);
			imm : In  std_logic_vector (7 DOWNTO 0);
			r7 : Out  std_logic_vector (7 DOWNTO 0);
			mar : Out  std_logic_vector (15 DOWNTO 0);
			mdr : InOut  std_logic_vector (15 DOWNTO 0);
			rd : Out  std_logic;
			wr : Out  std_logic;
			rz : Out  std_logic
		);
	END COMPONENT;

	SIGNAL ex : std_logic;
	SIGNAL opcode : std_logic_vector (3 DOWNTO 0);
	SIGNAL r1 : std_logic_vector (2 DOWNTO 0);
	SIGNAL r2 : std_logic_vector (2 DOWNTO 0);
	SIGNAL t : std_logic_vector (2 DOWNTO 0);
	SIGNAL imm : std_logic_vector (7 DOWNTO 0);
	SIGNAL r7 : std_logic_vector (7 DOWNTO 0);
	SIGNAL mar : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr : std_logic_vector (15 DOWNTO 0);
	SIGNAL rd : std_logic;
	SIGNAL wr : std_logic;
	SIGNAL rz : std_logic;

BEGIN
	UUT : exe
	PORT MAP (
		ex => ex,
		opcode => opcode,
		r1 => r1,
		r2 => r2,
		t => t,
		imm => imm,
		r7 => r7,
		mar => mar,
		mdr => mdr,
		rd => rd,
		wr => wr,
		rz => rz
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_r7(
			next_r7 : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (r7 /= next_r7) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns r7="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r7);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_r7);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_mar(
			next_mar : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mar /= next_mar) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns mar="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mar);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mar);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_rd(
			next_rd : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rd /= next_rd) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns rd="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rd);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rd);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_wr(
			next_wr : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (wr /= next_wr) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns wr="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wr);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wr);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_rz(
			next_rz : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rz /= next_rz) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns rz="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rz);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rz);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_mdr(
			next_mdr : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mdr /= next_mdr) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns mdr="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mdr);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0100"); --4
		-- --------------------
		WAIT FOR 1500 ns; -- Time=3500 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION exe_cfg OF wexe IS
	FOR testbench_arch
	END FOR;
END exe_cfg;
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -