__projnav.log

用VHDL 编写的一个16位的cpu 设计方案

Constraints file: cpu.pcf

Loading device database for application Par from file "cpu_map.ncd".
   "cpu" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-11-04.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            70 out of 166    42%
      Number of LOCed External IOBs   70 out of 70    100%

   Number of SLICEs                   42 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989896) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9a53cf) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file cpu.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 301 unrouted;       REAL time: 0 secs 

Phase 2: 263 unrouted;       REAL time: 0 secs 

Phase 3: 58 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   26   |  0.092     |  0.611      |
+----------------------------+----------+--------+------------+-------------+
|          u4_N8201          |   Local  |   45   |  1.491     |  4.365      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file cpu.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Thu Nov 03 18:26:06 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module cpu . . .
PAR command line: par -w -intstyle ise -ol std -t 1 cpu_map.ncd cpu.ncd cpu.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu/alu.vhd in Library work.
Architecture behavioral of Entity alu is up to date.
Compiling vhdl file F:/cpu/timer.vhd in Library work.
Architecture behavioral of Entity timer is up to date.
Compiling vhdl file F:/cpu/GetInstr.vhd in Library work.
Architecture behavioral of Entity getinstr is up to date.
Compiling vhdl file F:/cpu/exe.vhd in Library work.
Architecture behavioral of Entity exe is up to date.
Compiling vhdl file F:/cpu/memcontrol.vhd in Library work.
Architecture behavioral of Entity memcontrol is up to date.
Compiling vhdl file F:/cpu/cpu.vhd in Library work.
Architecture behavioral of Entity cpu is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cpu> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/cpu/cpu.vhd line 17: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - F:/cpu/cpu.vhd line 19: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <cpu> analyzed. Unit <cpu> generated.

Analyzing Entity <timer> (Architecture <behavioral>).
Entity <timer> analyzed. Unit <timer> generated.

Analyzing Entity <GetInstr> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <mdrout> in unit <GetInstr> never changes during circuit operation. The register is replaced by logic.
Entity <GetInstr> analyzed. Unit <GetInstr> generated.

Analyzing Entity <exe> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu/exe.vhd line 52: The following signals are missing in the process sensitivity list:
   opcode, imm, output, mdrin<7>, mdrin<6>, mdrin<5>, mdrin<4>, mdrin<3>, mdrin<2>, mdrin<1>, mdrin<0>.
Entity <exe> analyzed. Unit <exe> generated.

Analyzing Entity <alu> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.

Analyzing Entity <memcontrol> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu/memcontrol.vhd line 73: The following signals are missing in the process sensitivity list:
   ex.
Entity <memcontrol> analyzed. Unit <memcontrol> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alu>.
    Related source file is F:/cpu/alu.vhd.
WARNING:Xst:737 - Found 8-bit latch for signal <output>.
    Found 8-bit addsub for signal <$n0007>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <alu> synthesized.


Synthesizing Unit <memcontrol>.
    Related source file is F:/cpu/memcontrol.vhd.
WARNING:Xst:647 - Input <mdr0in> is never used.
WARNING:Xst:647 - Input <rd1> is never used.
WARNING:Xst:647 - Input <wr1> is never used.
    Register <nBLE> equivalent to <nMREQ> has been removed
    Register <s0> equivalent to <ABUS> has been removed
WARNING:Xst:737 - Found 16-bit latch for signal <mdr0out>.
WARNING:Xst:737 - Found 16-bit latch for signal <mdr1out>.
WARNING:Xst:737 - Found 16-bit latch for signal <ABUS>.
WARNING:Xst:737 - Found 16-bit latch for signal <DBUS>.
    Found 1-bit register for signal <nBHE>.
    Found 1-bit register for signal <nMREQ>.
    Found 1-bit register for signal <nRD>.
    Found 1-bit register for signal <nWR>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <memcontrol> synthesized.


Synthesizing Unit <exe>.
    Related source file is F:/cpu/exe.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <mdrin<15:8>> is never used.
WARNING:Xst:1305 - Output <mdrout<15:8>> is never assigned. Tied to value 00000000.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_0>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_7>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_6>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_5>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_4>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_3>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_2>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_15>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_14>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_13>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_12>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_11>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_10>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_9>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_8>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_0>.
    Found 1-bit tristate buffer for signal <rd>.
    Found 1-bit tristate buffer for signal <wr>.
    Found 8-bit 8-to-1 multiplexer for signal