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emcontrol> (Architecture <behavioral>).WARNING:Xst:819 - F:/cpu/memcontrol.vhd line 73: The following signals are missing in the process sensitivity list: ex.Entity <memcontrol> analyzed. Unit <memcontrol> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <memcontrol>. Related source file is F:/cpu/memcontrol.vhd.WARNING:Xst:647 - Input <mdr0in> is never used.WARNING:Xst:647 - Input <rd1> is never used.WARNING:Xst:647 - Input <wr1> is never used. Register <nBLE> equivalent to <nMREQ> has been removed Register <s0> equivalent to <ABUS> has been removedWARNING:Xst:737 - Found 16-bit latch for signal <mdr0out>.WARNING:Xst:737 - Found 16-bit latch for signal <mdr1out>.WARNING:Xst:737 - Found 16-bit latch for signal <ABUS>.WARNING:Xst:737 - Found 16-bit latch for signal <DBUS>. Found 1-bit register for signal <nMREQ>. Found 1-bit register for signal <nRD>. Found 1-bit register for signal <nWR>. Found 1-bit register for signal <nBHE>. Summary: inferred 4 D-type flip-flop(s).Unit <memcontrol> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Latches : 4 16-bit latch : 4==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <memcontrol> ...Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block memcontrol, actual ratio is 1.Latch DBUS_10 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_11 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_12 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_13 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_14 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_15 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_0 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_1 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_2 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_3 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_4 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_5 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_6 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_7 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_8 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_9 has been replicated 2 time(s) to handle iob=true attribute.FlipFlop nMREQ has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_15 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_14 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_13 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_12 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_11 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_10 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_9 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_8 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_7 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_6 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_5 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_4 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_3 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_2 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_1 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_0 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v200pq240-4 Number of Slices: 68 out of 2352 2% Number of Slice Flip Flops: 117 out of 4704 2% Number of 4 input LUTs: 40 out of 4704 0% Number of bonded IOBs: 154 out of 170 90% Number of GCLKs: 2 out of 4 50% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+N1598(Ker15961:O) | NONE(*)(DBUS_3_1) | 48 |N1618(Ker16161:O) | NONE(*)(ABUS_9) | 32 |ex | BUFGP | 32 |clk | BUFGP | 5 |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 14.456ns Maximum output required time after clock: 8.426ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
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Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/cpu/memcontrol.vhd in Library work.Architecture behavioral of Entity memcontrol is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <memcontrol> (Architecture <behavioral>).WARNING:Xst:819 - F:/cpu/memcontrol.vhd line 73: The following signals are missing in the process sensitivity list: ex.Entity <memcontrol> analyzed. Unit <memcontrol> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <memcontrol>. Related source file is F:/cpu/memcontrol.vhd.WARNING:Xst:647 - Input <mdr0in> is never used.WARNING:Xst:647 - Input <rd1> is never used.WARNING:Xst:647 - Input <wr1> is never used. Register <nBLE> equivalent to <nMREQ> has been removed Register <s0> equivalent to <ABUS> has been removedWARNING:Xst:737 - Found 16-bit latch for signal <mdr0out>.WARNING:Xst:737 - Found 16-bit latch for signal <mdr1out>.WARNING:Xst:737 - Found 16-bit latch for signal <ABUS>.WARNING:Xst:737 - Found 16-bit latch for signal <DBUS>. Found 1-bit register for signal <nMREQ>. Found 1-bit register for signal <nRD>. Found 1-bit register for signal <nWR>. Found 1-bit register for signal <nBHE>. Summary: inferred 4 D-type flip-flop(s).Unit <memcontrol> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Latches : 4 16-bit latch : 4==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <memcontrol> ...Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block memcontrol, actual ratio is 1.Latch DBUS_10 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_11 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_12 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_13 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_14 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_15 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_0 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_1 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_2 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_3 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_4 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_5 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_6 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_7 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_8 has been replicated 2 time(s) to handle iob=true attribute.Latch DBUS_9 has been replicated 2 time(s) to handle iob=true attribute.FlipFlop nMREQ has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_15 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_14 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_13 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_12 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_11 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_10 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_9 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_8 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_7 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_6 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_5 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_4 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_3 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_2 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_1 has been replicated 1 time(s) to handle iob=true attribute.Latch ABUS_0 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v200pq240-4 Number of Slices: 68 out of 2352 2% Number of Slice Flip Flops: 117 out of 4704 2% Number of 4 input LUTs: 40 out of 4704 0% Number of bonded IOBs: 154 out of 170 90% Number of GCLKs: 2 out of 4 50% =========================================================================TIMING REPORT⌨️ 快捷键说明
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