📄 cpu.twr
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Release 6.1i Trace G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml cpu cpu.ncd -o cpu.twr
cpu.pcf
Design file: cpu.ncd
Physical constraint file: cpu.pcf
Device,speed: xcv200,-4 (FINAL 1.123 2003-11-04)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
rst | 12.916(R)| -0.909(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
ABUS<0> | 22.769(R)|clk_BUFGP | 0.000|
ABUS<10> | 24.032(R)|clk_BUFGP | 0.000|
ABUS<11> | 23.577(R)|clk_BUFGP | 0.000|
ABUS<12> | 23.577(R)|clk_BUFGP | 0.000|
ABUS<13> | 23.578(R)|clk_BUFGP | 0.000|
ABUS<14> | 23.455(R)|clk_BUFGP | 0.000|
ABUS<15> | 23.155(R)|clk_BUFGP | 0.000|
ABUS<1> | 23.572(R)|clk_BUFGP | 0.000|
ABUS<2> | 23.572(R)|clk_BUFGP | 0.000|
ABUS<3> | 23.531(R)|clk_BUFGP | 0.000|
ABUS<4> | 21.785(R)|clk_BUFGP | 0.000|
ABUS<5> | 24.028(R)|clk_BUFGP | 0.000|
ABUS<6> | 24.028(R)|clk_BUFGP | 0.000|
ABUS<7> | 23.900(R)|clk_BUFGP | 0.000|
ABUS<8> | 22.496(R)|clk_BUFGP | 0.000|
ABUS<9> | 23.108(R)|clk_BUFGP | 0.000|
DBUS<0> | 23.717(R)|clk_BUFGP | 0.000|
DBUS<10> | 24.345(R)|clk_BUFGP | 0.000|
DBUS<11> | 24.080(R)|clk_BUFGP | 0.000|
DBUS<12> | 24.125(R)|clk_BUFGP | 0.000|
DBUS<13> | 24.125(R)|clk_BUFGP | 0.000|
DBUS<14> | 24.080(R)|clk_BUFGP | 0.000|
DBUS<15> | 24.080(R)|clk_BUFGP | 0.000|
DBUS<1> | 23.747(R)|clk_BUFGP | 0.000|
DBUS<2> | 24.439(R)|clk_BUFGP | 0.000|
DBUS<3> | 24.439(R)|clk_BUFGP | 0.000|
DBUS<4> | 24.439(R)|clk_BUFGP | 0.000|
DBUS<5> | 24.675(R)|clk_BUFGP | 0.000|
DBUS<6> | 24.365(R)|clk_BUFGP | 0.000|
DBUS<7> | 24.679(R)|clk_BUFGP | 0.000|
DBUS<8> | 23.826(R)|clk_BUFGP | 0.000|
DBUS<9> | 23.826(R)|clk_BUFGP | 0.000|
a3 | 21.762(R)|clk_BUFGP | 0.000|
a4 | 23.088(R)|clk_BUFGP | 0.000|
a5 | 17.263(R)|clk_BUFGP | 0.000|
a6 | 20.706(R)|clk_BUFGP | 0.000|
a7 | 22.956(R)|clk_BUFGP | 0.000|
b0 | 12.734(R)|clk_BUFGP | 0.000|
b1 | 12.986(R)|clk_BUFGP | 0.000|
b2 | 12.376(R)|clk_BUFGP | 0.000|
b3 | 12.296(R)|clk_BUFGP | 0.000|
b4 | 11.923(R)|clk_BUFGP | 0.000|
nBHE | 16.816(R)|clk_BUFGP | 0.000|
nBLE | 21.801(R)|clk_BUFGP | 0.000|
nMREQ | 22.028(R)|clk_BUFGP | 0.000|
nRD | 20.672(R)|clk_BUFGP | 0.000|
nWR | 21.046(R)|clk_BUFGP | 0.000|
s0<0> | 26.293(R)|clk_BUFGP | 0.000|
s0<10> | 27.587(R)|clk_BUFGP | 0.000|
s0<11> | 27.590(R)|clk_BUFGP | 0.000|
s0<12> | 26.317(R)|clk_BUFGP | 0.000|
s0<13> | 26.205(R)|clk_BUFGP | 0.000|
s0<14> | 26.205(R)|clk_BUFGP | 0.000|
s0<15> | 26.293(R)|clk_BUFGP | 0.000|
s0<1> | 25.586(R)|clk_BUFGP | 0.000|
s0<2> | 24.803(R)|clk_BUFGP | 0.000|
s0<3> | 24.803(R)|clk_BUFGP | 0.000|
s0<4> | 24.528(R)|clk_BUFGP | 0.000|
s0<5> | 24.528(R)|clk_BUFGP | 0.000|
s0<6> | 25.107(R)|clk_BUFGP | 0.000|
s0<7> | 25.107(R)|clk_BUFGP | 0.000|
s0<8> | 26.619(R)|clk_BUFGP | 0.000|
s0<9> | 26.619(R)|clk_BUFGP | 0.000|
s4<0> | 7.912(R)|clk_BUFGP | 0.000|
s4<1> | 7.912(R)|clk_BUFGP | 0.000|
s4<2> | 7.912(R)|clk_BUFGP | 0.000|
s4<3> | 7.912(R)|clk_BUFGP | 0.000|
s4<4> | 7.911(R)|clk_BUFGP | 0.000|
s4<5> | 7.912(R)|clk_BUFGP | 0.000|
s4<6> | 7.912(R)|clk_BUFGP | 0.000|
s4<7> | 7.912(R)|clk_BUFGP | 0.000|
s5<0> | 7.948(R)|clk_BUFGP | 0.000|
s5<1> | 7.980(R)|clk_BUFGP | 0.000|
s5<2> | 7.980(R)|clk_BUFGP | 0.000|
s5<3> | 7.911(R)|clk_BUFGP | 0.000|
s5<4> | 7.911(R)|clk_BUFGP | 0.000|
s5<5> | 7.912(R)|clk_BUFGP | 0.000|
s5<6> | 7.912(R)|clk_BUFGP | 0.000|
s5<7> | 7.911(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 18.477| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
DBUS<0> |s2<0> | 11.235|
DBUS<10> |s2<10> | 9.955|
DBUS<11> |s2<11> | 9.913|
DBUS<12> |s2<12> | 10.069|
DBUS<13> |s2<13> | 9.774|
DBUS<14> |s2<14> | 9.375|
DBUS<15> |s2<15> | 10.126|
DBUS<1> |s2<1> | 10.662|
DBUS<2> |s2<2> | 11.269|
DBUS<3> |s2<3> | 10.696|
DBUS<4> |s2<4> | 10.973|
DBUS<5> |s2<5> | 10.473|
DBUS<6> |s2<6> | 10.548|
DBUS<7> |s2<7> | 10.863|
DBUS<8> |s2<8> | 10.903|
DBUS<9> |s2<9> | 10.163|
---------------+---------------+---------+
Analysis completed Thu Nov 10 17:34:38 2005
--------------------------------------------------------------------------------
Peak Memory Usage: 49 MB
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