memcontrol.vhd

用VHDL 编写的一个16位的cpu 设计方案

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-- Company: 
-- Engineer:
--
-- Create Date:    17:53:19 10/19/05
-- Design Name:    
-- Module Name:    memcontrol - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity memcontrol is
port( t:in std_logic_vector(2 downto 0);
    	clk,rd1,wr1,rd2,wr2,ex:in std_logic;
		mdr0out,mdr1out,ABUS,s0,s2:out std_logic_vector(15 downto 0);
		mdr0in,mdr1in,mar0in,mar1in:in std_logic_vector(15 downto 0);
		DBUS:inout std_logic_vector(15 downto 0);
		--DBUSout:out std_logic_vector(15 downto 0);
		--:buffer std_logic;
		nMREQ,nRD,nWR,nBHE,nBLE,a7,a6,a5,a4,a3:out std_logic);
end memcontrol;

architecture Behavioral of memcontrol is

begin
	process(ex,rd1,rd2,wr2)
	  begin
	    if ex='0' and rd1='1'then
		   nRD<='0';nBHE<='0';nBLE<='0';nMREQ<='0';nWR<='1'; a6<='0';a5<='0';a4<='0';a7<='0';a3<='1';
	     elsif ex='1'  and rd2='1' then
		    nRD<='0';nBLE<='0';nMREQ<='0'; nWR<='1';nBHE<='1';	   a6<='0';a4<='0';a7<='0'; a3<='1';a5<='1';
		elsif ex='1' and wr2='1' then 
		    nWR<='0';nBLE<='0';nMREQ<='0';nRD<='1';nBHE<='1';
		    a3<='0';a4<='0';a7<='0';a6<='1';a5<='1';                   
		else  nMREQ<='1';nRD<='1';nWR<='1';nBHE<='1';nBLE<='1';
		      a7<='1';a6<='1';a3<='1';a4<='1';a5<='1';
		end if;
	end process;
  	
   ABUS<=mar0in when  ex='0' and rd1='1'and wr1='0'else
	    mar1in  when ex='1'and (rd2='1' or wr2='1') else
	    "ZZZZZZZZZZZZZZZZ";
   DBUS<=mdr1in when	ex='1' and wr2='1' else
	    "ZZZZZZZZZZZZZZZZ";
   s0<=mar0in when  ex='0' and rd1='1'and wr1='0'else
	    mar1in  when ex='1'and (rd2='1' or wr2='1') else
	    "ZZZZZZZZZZZZZZZZ";
   	
   process(DBUS)
	  begin
		  s2<=DBUS;
	     if ex='0' then 
		    mdr0out<=DBUS;	
       elsif ex='1'then
		    mdr1out<=DBUS;
       end if;
    end process;
   
end Behavioral;