timer.vhd

用VHDL 编写的一个16位的cpu 设计方案

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity timer is
port( clk,rst:in std_logic;
	ex,b0,b1,b2,b3,b4:out std_logic;
      t:out std_logic_vector(2 downto 0));
end timer;

architecture Behavioral of timer is
signal q:std_logic_vector(2 downto 0);
begin
	process(rst,clk)
	  begin
	   if rst='1' then q<="000";t<="100";ex<='0';
	   elsif clk'event and clk='1' then		
	   case q is
	   	when"000"=>q<="001";t<="100";ex<='0';b0<='1';b1<='0';b2<='0';b3<='0';b4<='0';
	     when"001"=>q<="010";t<="010";ex<='0';b0<='0';b1<='1';b2<='0';b3<='0';b4<='0';
	     when"010"=>q<="011";t<="001";ex<='0';b0<='0';b1<='0';b2<='1';b3<='0';b4<='0';
	     when"011"=>q<="100";t<="100";ex<='1';b0<='0';b1<='0';b2<='0';b3<='1';b4<='0';
	     when"100"=>q<="000";t<="010";ex<='1';b0<='0';b1<='0';b2<='0';b3<='0';b4<='1';
		when others=>NULL; 
	   end case;   
	   end if;
   end process;
end Behavioral;