wexe.ant

用VHDL 编写的一个16位的cpu 设计方案

-- F:\CPU
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:31:12 2005

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wexe IS
END wexe;

ARCHITECTURE testbench_arch OF wexe IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\cpu\wexe.ano";
	COMPONENT exe
		PORT (
			ex : In  std_logic;
			opcode : In  std_logic_vector (3 DOWNTO 0);
			r1 : In  std_logic_vector (2 DOWNTO 0);
			r2 : In  std_logic_vector (2 DOWNTO 0);
			t : In  std_logic_vector (2 DOWNTO 0);
			imm : In  std_logic_vector (7 DOWNTO 0);
			r7 : Out  std_logic_vector (7 DOWNTO 0);
			mar : Out  std_logic_vector (15 DOWNTO 0);
			mdr : InOut  std_logic_vector (15 DOWNTO 0);
			rd : Out  std_logic;
			wr : Out  std_logic;
			rz : Out  std_logic
		);
	END COMPONENT;

	SIGNAL ex : std_logic;
	SIGNAL opcode : std_logic_vector (3 DOWNTO 0);
	SIGNAL r1 : std_logic_vector (2 DOWNTO 0);
	SIGNAL r2 : std_logic_vector (2 DOWNTO 0);
	SIGNAL t : std_logic_vector (2 DOWNTO 0);
	SIGNAL imm : std_logic_vector (7 DOWNTO 0);
	SIGNAL r7 : std_logic_vector (7 DOWNTO 0);
	SIGNAL mar : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr : std_logic_vector (15 DOWNTO 0);
	SIGNAL rd : std_logic;
	SIGNAL wr : std_logic;
	SIGNAL rz : std_logic;

BEGIN
	UUT : exe
	PORT MAP (
		ex => ex,
		opcode => opcode,
		r1 => r1,
		r2 => r2,
		t => t,
		imm => imm,
		r7 => r7,
		mar => mar,
		mdr => mdr,
		rd => rd,
		wr => wr,
		rz => rz
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_r7(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",r7,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r7);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_mar(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",mar,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mar);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_rd(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rd,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rd);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_wr(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",wr,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wr);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_rz(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rz,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rz);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_mdr(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",mdr,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_r7(TX_TIME);
		ANNOTATE_mar(TX_TIME);
		ANNOTATE_rd(TX_TIME);
		ANNOTATE_wr(TX_TIME);
		ANNOTATE_rz(TX_TIME);
		ANNOTATE_mdr(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		opcode <= transport std_logic_vector'("0111"); --7
		r1 <= transport std_logic_vector'("001"); --1
		r2 <= transport std_logic_vector'("000"); --0
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		opcode <= transport std_logic_vector'("0000"); --0
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("001"); --1
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		ex <= transport '1';
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("100"); --4
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		opcode <= transport std_logic_vector'("0001"); --1
		r1 <= transport std_logic_vector'("111"); --7
		r2 <= transport std_logic_vector'("001"); --1
		t <= transport std_logic_vector'("010"); --2
		imm <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		ex <= transport '0';
		opcode <= transport std_logic_vector'("0100"); --4
		-- --------------------
		WAIT FOR 1500 ns; -- Time=3500 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION exe_cfg OF wexe IS
	FOR testbench_arch
	END FOR;
END exe_cfg;