exe.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: exe.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : exe.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : exe
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : exe
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : exe.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu1/alu.vhd in Library work.
Architecture behavioral of Entity alu is up to date.
Compiling vhdl file F:/cpu1/exe.vhd in Library work.
Architecture behavioral of Entity exe is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <exe> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu1/exe.vhd line 52: The following signals are missing in the process sensitivity list:
   opcode, imm, output, mdrin<7>, mdrin<6>, mdrin<5>, mdrin<4>, mdrin<3>, mdrin<2>, mdrin<1>, mdrin<0>.
Entity <exe> analyzed. Unit <exe> generated.

Analyzing Entity <alu> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alu>.
    Related source file is F:/cpu1/alu.vhd.
WARNING:Xst:737 - Found 8-bit latch for signal <output>.
    Found 8-bit addsub for signal <$n0007>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <alu> synthesized.


Synthesizing Unit <exe>.
    Related source file is F:/cpu1/exe.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <mdrin<15:8>> is never used.
WARNING:Xst:1306 - Output <mdrout<15:8>> is never assigned.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_0>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_7>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_6>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_5>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_4>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_3>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_2>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_15>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_14>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_13>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_12>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_11>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_10>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_9>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_8>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_0>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0001> created at line 62.
    Found 8-bit 8-to-1 multiplexer for signal <$n0003> created at line 62.
    Found 104 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 120 Multiplexer(s).
Unit <exe> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 35
  8-bit latch                      : 11
  1-bit latch                      : 24
# Multiplexers                     : 37
  2-to-1 multiplexer               : 35
  8-bit 8-to-1 multiplexer         : 2
# Adders/Subtractors               : 1
  8-bit addsub                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <exe> ...

Optimizing unit <alu> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block exe, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : exe.ngr
Top Level Output File Name         : exe
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 82

Macro Statistics :
# Multiplexers                     : 37
#      2-to-1 multiplexer          : 35
#      8-bit 8-to-1 multiplexer    : 2
# Adders/Subtractors               : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 347
#      LUT2                        : 11
#      LUT3                        : 48
#      LUT3_L                      : 72
#      LUT4                        : 138
#      LUT4_L                      : 15
#      MUXCY                       : 7
#      MUXF5                       : 32
#      MUXF6                       : 16
#      XORCY                       : 8
# FlipFlops/Latches                : 112