📄 cpu.mrp
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| DBUS<12> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<13> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<14> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<15> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || a3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || a4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || a5 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || a6 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || a7 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || b0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || b1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || b2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || b3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || b4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nBHE | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nBLE | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nMREQ | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nRD | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nWR | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || rst | IOB | INPUT | LVTTL | | | | | || s0<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s0<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s2<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || s4<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s4<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || s5<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 97Number of Equivalent Gates for Design = 4,017Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 99IOB Latches not driven by LUTs = 16IOB Latches = 16IOB Flip Flops not driven by LUTs = 16IOB Flip Flops = 16Unbonded IOBs = 0Bonded IOBs = 96Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 484 input LUTs used as Route-Thrus = 144 input LUTs = 348Slice Latches not driven by LUTs = 8Slice Latches = 120Slice Flip Flops not driven by LUTs = 59Slice Flip Flops = 88Slices = 223Number of LUT signals with 4 loads = 2Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 33Number of LUT signals with 1 load = 272NGM Average fanout of LUT = 2.49NGM Maximum fanout of LUT = 67NGM Average fanin for LUT = 3.4310Number of LUT symbols = 348Number of IPAD symbols = 2Number of IBUF symbols = 17Number of BIPAD symbols = 16⌨️ 快捷键说明
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