📄 cpu.mrp
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Release 6.1i Map G.26Xilinx Mapping Report File for Design 'cpu'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv200-pq240-4 -cm
area -pr b -k 4 -c 100 -tx off -o cpu_map.ncd cpu.ngd cpu.pcf Target Device : xv200Target Package : pq240Target Speed : -4Mapper Version : virtex -- $Revision: 1.16 $Mapped Date : Thu Nov 10 17:34:29 2005Design Summary--------------Number of errors: 0Number of warnings: 2Logic Utilization: Total Number Slice Registers: 208 out of 4,704 4% Number used as Flip Flops: 88 Number used as Latches: 120 Number of 4 input LUTs: 348 out of 4,704 7%Logic Distribution: Number of occupied Slices: 223 out of 2,352 9% Number of Slices containing only related logic: 223 out of 223 100% Number of Slices containing unrelated logic: 0 out of 223 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 362 out of 4,704 7% Number used as logic: 348 Number used as a route-thru: 14 Number of bonded IOBs: 96 out of 166 57% IOB Flip Flops: 16 IOB Latches: 16 Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 4,017Additional JTAG gate count for IOBs: 4,656Peak Memory Usage: 64 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u3_u1__n0002 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u3__n0096 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || ABUS<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ABUS<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || DBUS<0> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<1> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<2> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<3> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<4> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<5> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<6> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<7> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<8> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<9> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<10> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD || DBUS<11> | IOB | BIDIR | LVTTL | 12 | SLOW | INLATCH | | IFD |⌨️ 快捷键说明
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