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📄 getinstr.mrp

📁 用VHDL 编写的一个16位的cpu 设计方案
💻 MRP
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To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || clr                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       || ex                                 | IOB     | INPUT     | LVTTL       |          |      |          |          |       || imm<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<6>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || imm<7>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || mar<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<6>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<7>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<8>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<9>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<10>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<11>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<12>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<13>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<14>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mar<15>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || mdrin<1>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<2>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<3>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<4>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<5>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<6>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<7>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<8>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<9>                           | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<10>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<11>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<12>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<13>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<14>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || mdrin<15>                          | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   || opcode<0>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || opcode<1>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || opcode<2>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || opcode<3>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || r1<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || r1<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || r1<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || r2<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || r2<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || r2<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || r7<0>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<1>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<2>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<3>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<4>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<5>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<6>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || r7<7>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       || rd                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || rz                                 | IOB     | INPUT     | LVTTL       |          |      |          |          |       || t<0>                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       || t<1>                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       || t<2>                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 65Number of Equivalent Gates for Design = 766Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 46IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 38IOB Flip Flops = 38Unbonded IOBs = 0Bonded IOBs = 64Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 144 input LUTs = 23Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 8Slice Flip Flops = 24Slices = 23Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 1Number of LUT signals with 1 load = 18NGM Average fanout of LUT = 3.57NGM Maximum fanout of LUT = 16NGM Average fanin for LUT = 2.9565Number of LUT symbols = 23Number of IPAD symbols = 30Number of IBUF symbols = 29

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