getinstr.mrp

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i Map G.26
Xilinx Mapping Report File for Design 'getinstr'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv200-pq240-4 -cm
area -pr b -k 4 -c 100 -tx off -o getinstr_map.ncd getinstr.ngd getinstr.pcf 
Target Device  : xv200
Target Package : pq240
Target Speed   : -4
Mapper Version : virtex -- $Revision: 1.16 $
Mapped Date    : Thu Nov 03 16:39:20 2005

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        24 out of  4,704    1%
  Number of 4 input LUTs:            23 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                          23 out of  2,352    1%
    Number of Slices containing only related logic:     23 out of     23  100%
    Number of Slices containing unrelated logic:         0 out of     23    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           37 out of  4,704    1%
      Number used as logic:                        23
      Number used as a route-thru:                 14
   Number of bonded IOBs:            64 out of    166   38%
      IOB Flip Flops:                              38
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  766
Additional JTAG gate count for IOBs:  3,120
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------
  32 block(s) removed
   2 block(s) optimized away
  16 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "mdrout<3>" is unused and has been removed.
 Unused block "mdrout_3_OBUFT" (TRI) removed.
The signal "mdrout<0>" is unused and has been removed.
 Unused block "mdrout_0_OBUFT" (TRI) removed.
The signal "mdrout<4>" is unused and has been removed.
 Unused block "mdrout_4_OBUFT" (TRI) removed.
The signal "mdrout<1>" is unused and has been removed.
 Unused block "mdrout_1_OBUFT" (TRI) removed.
The signal "mdrout<2>" is unused and has been removed.
 Unused block "mdrout_2_OBUFT" (TRI) removed.
The signal "mdrout<5>" is unused and has been removed.
 Unused block "mdrout_5_OBUFT" (TRI) removed.
The signal "mdrout<6>" is unused and has been removed.
 Unused block "mdrout_6_OBUFT" (TRI) removed.
The signal "mdrout<15>" is unused and has been removed.
 Unused block "mdrout_15_OBUFT" (TRI) removed.
The signal "mdrout<14>" is unused and has been removed.
 Unused block "mdrout_14_OBUFT" (TRI) removed.
The signal "mdrout<13>" is unused and has been removed.
 Unused block "mdrout_13_OBUFT" (TRI) removed.
The signal "mdrout<12>" is unused and has been removed.
 Unused block "mdrout_12_OBUFT" (TRI) removed.
The signal "mdrout<11>" is unused and has been removed.
 Unused block "mdrout_11_OBUFT" (TRI) removed.
The signal "mdrout<10>" is unused and has been removed.
 Unused block "mdrout_10_OBUFT" (TRI) removed.
The signal "mdrout<9>" is unused and has been removed.
 Unused block "mdrout_9_OBUFT" (TRI) removed.
The signal "mdrout<8>" is unused and has been removed.
 Unused block "mdrout_8_OBUFT" (TRI) removed.
The signal "mdrout<7>" is unused and has been removed.
 Unused block "mdrout_7_OBUFT" (TRI) removed.
Unused block "mdrout<0>" (PAD) removed.
Unused block "mdrout<10>" (PAD) removed.
Unused block "mdrout<11>" (PAD) removed.
Unused block "mdrout<12>" (PAD) removed.
Unused block "mdrout<13>" (PAD) removed.
Unused block "mdrout<14>" (PAD) removed.
Unused block "mdrout<15>" (PAD) removed.
Unused block "mdrout<1>" (PAD) removed.
Unused block "mdrout<2>" (PAD) removed.
Unused block "mdrout<3>" (PAD) removed.
Unused block "mdrout<4>" (PAD) removed.
Unused block "mdrout<5>" (PAD) removed.
Unused block "mdrout<6>" (PAD) removed.
Unused block "mdrout<7>" (PAD) removed.
Unused block "mdrout<8>" (PAD) removed.
Unused block "mdrout<9>" (PAD) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC