alu.vhd

用VHDL 编写的一个16位的cpu 设计方案

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-- Company: 
-- Engineer:
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-- Create Date:    10:32:27 10/15/05
-- Design Name:    
-- Module Name:    execontrol - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu is
port( input1,input2 :in std_logic_vector(7 downto 0);
		opreg:in std_logic_vector(3 downto 0);
      output:out std_logic_vector(7 downto 0));
end alu;

architecture Behavioral of alu is

begin
  process(input1,input2,opreg)
    begin
	  if opreg="0000" then output<=input1+input2;
	  elsif opreg="0001" then output<=input1-input2;
	  elsif opreg="0010" or opreg="0111" then output<=input1;
	  end if ;
  end process;
				
end Behavioral;