timer.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: timer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : timer.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : timer
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : timer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : timer.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu1/timer.vhd in Library work.
Architecture behavioral of Entity timer is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <timer> (Architecture <behavioral>).
Entity <timer> analyzed. Unit <timer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <timer>.
    Related source file is F:/cpu1/timer.vhd.
    Found finite state machine <FSM_0> for signal <q>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <ex>.
    Found 1-bit register for signal <b0>.
    Found 1-bit register for signal <b1>.
    Found 1-bit register for signal <b2>.
    Found 1-bit register for signal <b3>.
    Found 1-bit register for signal <b4>.
    Found 3-bit register for signal <t>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   6 D-type flip-flop(s).
Unit <timer> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 7
  3-bit register                   : 1
  1-bit register                   : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <q> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <timer> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block timer, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : timer.ngr
Top Level Output File Name         : timer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 11

Macro Statistics :
# Registers                        : 9
#      1-bit register              : 9

Cell Usage :
# BELS                             : 19
#      LUT1                        : 1
#      LUT3_L                      : 9
#      LUT4_L                      : 9
# FlipFlops/Latches                : 14
#      FDC                         : 7
#      FDE                         : 5
#      FDP                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 10
#      IBUF                        : 1
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                      12  out of   2352     0%  
 Number of Slice Flip Flops:            14  out of   4704     0%  
 Number of 4 input LUTs:                19  out of   4704     0%  
 Number of bonded IOBs:                 10  out of    170     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 14    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.133ns (Maximum Frequency: 163.052MHz)
   Minimum input arrival time before clock: 7.009ns
   Maximum output required time after clock: 8.498ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               6.133ns (Levels of Logic = 2)
  Source:            q_FFd2 (FF)
  Destination:       t_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: q_FFd2 to t_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             10   1.372   2.420  q_FFd2 (q_FFd2)
     LUT3_L:I0->LO         1   0.738   0.100  _n0012_SW9 (N504)
     LUT4_L:I3->LO         1   0.738   0.000  _n00071 (_n0007)
     FDE:D                     0.765          b0
    ----------------------------------------
    Total                      6.133ns (3.613ns logic, 2.520ns route)
                                       (58.9% logic, 41.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              7.009ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       b0 (FF)
  Destination Clock: clk rising

  Data Path: rst to b0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.989   2.420  rst_IBUF (rst_IBUF)
     LUT1:I0->O            5   0.738   1.914  b4_N501 (b4_N50)
     FDE:CE                    0.948          b4
    ----------------------------------------
    Total                      7.009ns (2.675ns logic, 4.334ns route)
                                       (38.2% logic, 61.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              8.498ns (Levels of Logic = 1)
  Source:            ex (FF)
  Destination:       ex (PAD)
  Source Clock:      clk rising

  Data Path: ex to ex
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.372   1.474  ex (ex_OBUF)
     OBUF:I->O                 5.652          ex_OBUF (ex)
    ----------------------------------------
    Total                      8.498ns (7.024ns logic, 1.474ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
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Total memory usage is 57024 kilobytes