exe.vhd

用VHDL 编写的一个16位的cpu 设计方案

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-- Company: 
-- Engineer:
--
-- Create Date:    15:50:01 10/19/05
-- Design Name:    
-- Module Name:    ex - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exe is
port( clk,ex:in std_logic;
      opcode:in std_logic_vector(3 downto 0);
		r1,r2,t:in std_logic_vector(2 downto 0);
		imm:in std_logic_vector(7 downto 0);
		r7:out std_logic_vector(7 downto 0);
		mar:out std_logic_vector(15 downto 0);
		mdrin:in std_logic_vector(15 downto 0);
		mdrout:out std_logic_vector(15 downto 0);
		rd,wr,rz:out std_logic);
end exe;

architecture Behavioral of exe is
type reg88 is array(7 downto 0) of std_logic_vector(7 downto 0);
signal input1,input2,output:std_logic_vector(7 downto 0);
component alu is
port( input1,input2 :in std_logic_vector(7 downto 0);
		opreg:in std_logic_vector(3 downto 0);
      output:out std_logic_vector(7 downto 0));
end component alu;
begin
	u1:alu port map(input1,input2,opcode,output);
	process(ex,t,clk)
	 variable reg:reg88;
	 begin
	   rd<='0';wr<='0';
	   rz<='0';
		r7<=reg(7);
	     if ex='1'then
		 case t is
		   when"100"=>
			   case opcode is
				  when"0000"|"0001"=>input1<=reg(conv_integer(r1));input2<=reg(conv_integer(r2));
				  when"0010"=>input1<=reg(conv_integer(r2));
				  when"0111"=>input1<=imm;
				  when"0011"=>mar(15 downto 8)<=reg(7); mar(7 downto 0)<=imm;rd<='1';wr<='0';
				  when"0100"=>mar(15 downto 8)<=reg(7); mar(7 downto 0)<=imm;mdrout(7 downto 0)<=reg(conv_integer(r1));
				  when others=>NULL;
				end case;
            when"010"=>
			   case opcode is
				  when"0000"|"0001"|"0010"|"0111"=>reg(conv_integer(r1)):=output;	
				  when"0011"=>reg(conv_integer(r1)):=mdrin(7 downto 0);
				  when"0100"=>wr<='1';rd<='0';
				  when"0101"=>
				    if reg(conv_integer(r1))="00000000" then rz<='1';
				    end if;
				  when"0110"=>rz<='1';
				  when others=>NULL;
				end case;
            when others=>NULL;
           end case;
		else NULL;
	    end if;
 --    end if;
	end process;
end Behavioral;