memcontrol.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: memcontrol.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : memcontrol.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : memcontrol
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : memcontrol
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : memcontrol.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu1/memcontrol.vhd in Library work.
Entity <memcontrol> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <memcontrol> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu1/memcontrol.vhd line 67: The following signals are missing in the process sensitivity list:
   ex.
Entity <memcontrol> analyzed. Unit <memcontrol> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <memcontrol>.
    Related source file is F:/cpu1/memcontrol.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <t> is never used.
WARNING:Xst:647 - Input <mdr0in> is never used.
WARNING:Xst:737 - Found 16-bit latch for signal <mdr0out>.
WARNING:Xst:737 - Found 16-bit latch for signal <mdr1out>.
    Found 16-bit tristate buffer for signal <ABUS>.
    Found 16-bit tristate buffer for signal <s0>.
    Found 16-bit tristate buffer for signal <DBUS>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  16 Multiplexer(s).
	inferred  48 Tristate(s).
Unit <memcontrol> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 2
  16-bit latch                     : 2
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Tristates                        : 3
  16-bit tristate buffer           : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <memcontrol> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block memcontrol, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : memcontrol.ngr
Top Level Output File Name         : memcontrol
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 179

Macro Statistics :
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1
# Tristates                        : 3
#      16-bit tristate buffer      : 3

Cell Usage :
# BELS                             : 23
#      LUT2                        : 2
#      LUT3                        : 19
#      LUT4                        : 2
# FlipFlops/Latches                : 32
#      LD                          : 16
#      LD_1                        : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 158
#      IBUF                        : 52
#      IOBUF                       : 16
#      OBUF                        : 58
#      OBUFT                       : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                      18  out of   2352     0%  
 Number of Slice Flip Flops:            32  out of   4704     0%  
 Number of 4 input LUTs:                23  out of   4704     0%  
 Number of bonded IOBs:                158  out of    170    92%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
ex                                 | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.426ns
   Maximum combinational path delay: 20.136ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'ex'
Offset:              8.426ns (Levels of Logic = 1)
  Source:            mdr0out_15 (LATCH)
  Destination:       mdr0out<15> (PAD)
  Source Clock:      ex rising

  Data Path: mdr0out_15 to mdr0out<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   1.509   1.265  mdr0out_15 (mdr0out_15)
     OBUF:I->O                 5.652          mdr0out_15_OBUF (mdr0out<15>)
    ----------------------------------------
    Total                      8.426ns (7.161ns logic, 1.265ns route)
                                       (85.0% logic, 15.0% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               20.136ns (Levels of Logic = 4)
  Source:            ex (PAD)
  Destination:       ABUS<15> (PAD)

  Data Path: ex to ABUS<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           39   0.885   4.565  ex_BUFGP (ex_BUFGP)
     LUT3:I1->O           17   0.738   3.190  _n00101 (_n0010)
     LUT4:I0->O           32   0.738   4.180  _n00161 (_n0016)
     OBUFT:T->O                5.840          ABUS_0_OBUFT (ABUS<0>)
    ----------------------------------------
    Total                     20.136ns (8.201ns logic, 11.935ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
CPU : 1.89 / 3.42 s | Elapsed : 2.00 / 4.00 s
 
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Total memory usage is 57024 kilobytes