wmemcontrol.vhw

用VHDL 编写的一个16位的cpu 设计方案

			END IF;
		END;

		PROCEDURE CHECK_mdr1out(
			next_mdr1out : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mdr1out /= next_mdr1out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns mdr1out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr1out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mdr1out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_ABUS(
			next_ABUS : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (ABUS /= next_ABUS) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns ABUS="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ABUS);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ABUS);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_s0(
			next_s0 : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s0 /= next_s0) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s0="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s0);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s0);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_s2(
			next_s2 : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s2 /= next_s2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_DBUS(
			next_DBUS : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (DBUS /= next_DBUS) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns DBUS="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DBUS);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DBUS);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		wr2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001011"); --B
		rd2 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001011"); --B
		rd2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010101"); --15
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001100"); --C
		wr2 <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001100"); --C
		wr2 <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010110"); --16
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001101"); --D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001101"); --D
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		t <= transport std_logic_vector'("010"); --2
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		t <= transport std_logic_vector'("001"); --1
		mdr0in <= transport std_logic_vector'("0000000000010111"); --17
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		mar0in <= transport std_logic_vector'("0000000000001110"); --E
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		t <= transport std_logic_vector'("010"); --2
		mar0in <= transport std_logic_vector'("0000000000001110"); --E
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		ex <= transport '0';
		-- --------------------
		WAIT FOR 650 ns; -- Time=2650 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION memcontrol_cfg OF wmemcontrol IS
	FOR testbench_arch
	END FOR;
END memcontrol_cfg;