cpu.par

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

hit57::  Thu Nov 10 17:34:33 2005


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 cpu_map.ncd cpu.ncd
cpu.pcf 


Constraints file: cpu.pcf

Loading device database for application Par from file "cpu_map.ncd".
   "cpu" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-11-04.


Resolved that IOB <s0<10>> must be placed at site P232.
Resolved that IOB <s0<11>> must be placed at site P231.
Resolved that IOB <s0<12>> must be placed at site P230.
Resolved that IOB <s0<13>> must be placed at site P229.
Resolved that IOB <b0> must be placed at site P125.
Resolved that IOB <b1> must be placed at site P124.
Resolved that IOB <a3> must be placed at site P177.
Resolved that IOB <s0<14>> must be placed at site P228.
Resolved that IOB <b2> must be placed at site P109.
Resolved that IOB <a4> must be placed at site P184.
Resolved that IOB <b3> must be placed at site P108.
Resolved that IOB <a5> must be placed at site P178.
Resolved that IOB <s0<15>> must be placed at site P224.
Resolved that IOB <b4> must be placed at site P107.
Resolved that IOB <a6> must be placed at site P152.
Resolved that IOB <a7> must be placed at site P147.
Resolved that IOB <s2<10>> must be placed at site P17.
Resolved that IOB <s2<11>> must be placed at site P13.
Resolved that IOB <s2<12>> must be placed at site P12.
Resolved that IOB <ABUS<10>> must be placed at site P185.
Resolved that IOB <s2<13>> must be placed at site P11.
Resolved that IOB <ABUS<11>> must be placed at site P208.
Resolved that IOB <s2<14>> must be placed at site P10.
Resolved that IOB <ABUS<12>> must be placed at site P207.
Resolved that IOB <s2<15>> must be placed at site P9.
Resolved that IOB <ABUS<13>> must be placed at site P206.
Resolved that IOB <ABUS<14>> must be placed at site P205.
Resolved that IOB <ABUS<15>> must be placed at site P187.
Resolved that IOB <nBHE> must be placed at site P189.
Resolved that IOB <nBLE> must be placed at site P191.
Resolved that IOB <s0<0>> must be placed at site P223.
Resolved that IOB <s0<1>> must be placed at site P222.
Resolved that IOB <s0<2>> must be placed at site P221.
Resolved that IOB <s0<3>> must be placed at site P220.
Resolved that IOB <s0<4>> must be placed at site P218.
Resolved that IOB <s0<5>> must be placed at site P217.
Resolved that IOB <s0<6>> must be placed at site P216.
Resolved that IOB <s0<7>> must be placed at site P215.
Resolved that IOB <s2<0>> must be placed at site P7.
Resolved that IOB <s0<8>> must be placed at site P235.
Resolved that IOB <s2<1>> must be placed at site P6.
Resolved that IOB <s0<9>> must be placed at site P234.
Resolved that IOB <ABUS<0>> must be placed at site P153.
Resolved that IOB <s2<2>> must be placed at site P5.
Resolved that IOB <ABUS<1>> must be placed at site P154.
Resolved that IOB <s2<3>> must be placed at site P4.
Resolved that IOB <ABUS<2>> must be placed at site P155.
Resolved that IOB <s2<4>> must be placed at site P3.
Resolved that IOB <ABUS<3>> must be placed at site P156.
Resolved that IOB <s2<5>> must be placed at site P238.
Resolved that IOB <ABUS<4>> must be placed at site P157.
Resolved that IOB <s2<6>> must be placed at site P237.
Resolved that IOB <ABUS<5>> must be placed at site P173.
Resolved that IOB <s2<7>> must be placed at site P236.
Resolved that IOB <ABUS<6>> must be placed at site P174.
Resolved that IOB <s2<8>> must be placed at site P19.
Resolved that IOB <s4<0>> must be placed at site P28.
Resolved that IOB <ABUS<7>> must be placed at site P175.
Resolved that IOB <s2<9>> must be placed at site P18.
Resolved that IOB <s4<1>> must be placed at site P27.
Resolved that IOB <ABUS<8>> must be placed at site P176.
Resolved that IOB <s4<2>> must be placed at site P26.
Resolved that IOB <ABUS<9>> must be placed at site P186.
Resolved that IOB <s4<3>> must be placed at site P25.
Resolved that IOB <s5<0>> must be placed at site P74.
Resolved that IOB <s4<4>> must be placed at site P24.
Resolved that IOB <s5<1>> must be placed at site P68.
Resolved that IOB <s4<5>> must be placed at site P23.
Resolved that IOB <s4<6>> must be placed at site P21.
Resolved that IOB <s5<2>> must be placed at site P67.
Resolved that IOB <s5<3>> must be placed at site P57.
Resolved that IOB <s4<7>> must be placed at site P20.
Resolved that IOB <s5<4>> must be placed at site P52.
Resolved that IOB <s5<5>> must be placed at site P46.
Resolved that IOB <s5<6>> must be placed at site P42.
Resolved that IOB <DBUS<10>> must be placed at site P200.
Resolved that IOB <s5<7>> must be placed at site P31.
Resolved that IOB <DBUS<11>> must be placed at site P199.
Resolved that IOB <DBUS<12>> must be placed at site P195.
Resolved that IOB <DBUS<13>> must be placed at site P194.
Resolved that IOB <DBUS<14>> must be placed at site P193.
Resolved that IOB <DBUS<15>> must be placed at site P192.
Resolved that IOB <nRD> must be placed at site P188.
Resolved that IOB <nWR> must be placed at site P171.
Resolved that GCLKIOB <clk> must be placed at site P92.
Resolved that IOB <rst> must be placed at site P33.
Resolved that IOB <DBUS<0>> must be placed at site P160.
Resolved that IOB <DBUS<1>> must be placed at site P161.
Resolved that IOB <DBUS<2>> must be placed at site P162.
Resolved that IOB <DBUS<3>> must be placed at site P163.
Resolved that IOB <DBUS<4>> must be placed at site P167.
Resolved that IOB <DBUS<5>> must be placed at site P168.
Resolved that IOB <DBUS<6>> must be placed at site P169.
Resolved that IOB <DBUS<7>> must be placed at site P170.
Resolved that IOB <DBUS<8>> must be placed at site P202.
Resolved that IOB <DBUS<9>> must be placed at site P201.
Resolved that IOB <nMREQ> must be placed at site P159.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            96 out of 166    57%
      Number of LOCed External IOBs   96 out of 96    100%

   Number of SLICEs                  223 out of 2352    9%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989e90) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.........
Phase 5.8 (Checksum:b48515) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file cpu.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1802 unrouted;       REAL time: 0 secs 

Phase 2: 1681 unrouted;       REAL time: 2 secs 

Phase 3: 556 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   66   |  0.100     |  0.611      |
+----------------------------+----------+--------+------------+-------------+
|           u1_ex_3          |   Local  |   60   |  2.586     |  6.497      |
+----------------------------+----------+--------+------------+-------------+
|      u3_u1__n0002          |   Local  |    8   |  0.037     |  3.530      |
+----------------------------+----------+--------+------------+-------------+
|           u1_ex_2          |   Local  |   48   |  2.207     |  4.502      |
+----------------------------+----------+--------+------------+-------------+
|         u3__n0096          |   Local  |   28   |  1.358     |  4.440      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 403


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.697
   The MAXIMUM PIN DELAY IS:                               7.685
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.676

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
         203         533         343         348         375           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file cpu.ncd.


PAR done.