alu.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: alu.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : alu.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : alu
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : alu
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : alu.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu/alu.vhd in Library work.
Architecture behavioral of Entity alu is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alu>.
    Related source file is F:/cpu/alu.vhd.
WARNING:Xst:737 - Found 8-bit latch for signal <output>.
    Found 8-bit addsub for signal <$n0007>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <alu> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 1
  8-bit latch                      : 1
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 1
  8-bit addsub                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <alu> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block alu, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : alu.ngr
Top Level Output File Name         : alu
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 28

Macro Statistics :
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1
# Adders/Subtractors               : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 50
#      LUT3                        : 17
#      LUT4                        : 18
#      MUXCY                       : 7
#      XORCY                       : 8
# FlipFlops/Latches                : 8
#      LDCP                        : 8
# IO Buffers                       : 28
#      IBUF                        : 20
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                      18  out of   2352     0%  
 Number of Slice Flip Flops:             8  out of   4704     0%  
 Number of 4 input LUTs:                35  out of   4704     0%  
 Number of bonded IOBs:                 28  out of    170    16%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0002(_n00021:O)                  | NONE(*)(output_5)      | 8     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 13.060ns
   Maximum output required time after clock: 8.426ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00021:O'
Offset:              13.060ns (Levels of Logic = 12)
  Source:            opreg<1> (PAD)
  Destination:       output_7 (LATCH)
  Destination Clock: _n00021:O falling

  Data Path: opreg<1> to output_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   0.989   3.410  opreg_1_IBUF (opreg_1_IBUF)
     LUT4:I0->O            9   0.738   2.332  _n00061 (_n0006)
     LUT3:I2->O            1   0.738   0.000  Maddsub__n0007_inst_lut3_01 (Maddsub__n0007_inst_lut3_0)
     MUXCY:S->O            1   0.842   0.000  Maddsub__n0007_inst_cy_0 (Maddsub__n0007_inst_cy_0)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0007_inst_cy_1 (Maddsub__n0007_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0007_inst_cy_2 (Maddsub__n0007_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0007_inst_cy_3 (Maddsub__n0007_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0007_inst_cy_4 (Maddsub__n0007_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  Maddsub__n0007_inst_cy_5 (Maddsub__n0007_inst_cy_5)
     MUXCY:CI->O           0   0.057   0.000  Maddsub__n0007_inst_cy_6 (Maddsub__n0007_inst_cy_6)
     XORCY:CI->O           3   0.538   1.628  Maddsub__n0007_inst_sum_7 (_n0012<15>)
     LUT3:I0->O            1   0.738   0.000  Mmux__n0004_Result<7>1 (_n0004<7>)
     LDCP:D                    0.765          output_7
    ----------------------------------------
    Total                     13.060ns (5.690ns logic, 7.370ns route)
                                       (43.6% logic, 56.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00021:O'
Offset:              8.426ns (Levels of Logic = 1)
  Source:            output_7 (LATCH)
  Destination:       output<7> (PAD)
  Source Clock:      _n00021:O falling

  Data Path: output_7 to output<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             1   1.509   1.265  output_7 (output_7)
     OBUF:I->O                 5.652          output_7_OBUF (output<7>)
    ----------------------------------------
    Total                      8.426ns (7.161ns logic, 1.265ns route)
                                       (85.0% logic, 15.0% route)

=========================================================================
CPU : 0.97 / 1.33 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 57024 kilobytes