cpu.syr

用VHDL 编写的一个16位的cpu 设计方案

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_13> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_15> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_14> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_8> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_9> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_10> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_11> is unconnected in block <cpu>.
WARNING:Xst:1291 - FF/Latch <u4_mdr1out_12> is unconnected in block <cpu>.
Building and optimizing final netlist ...
Register u2_r2_2 equivalent to u2_imm_7 has been removed
Register u2_ir_7 equivalent to u2_s4_7 has been removed
Register u2_ir_15 equivalent to u2_s5_7 has been removed
Register u2_r2_0 equivalent to u2_imm_5 has been removed
Register u2_r2_1 equivalent to u2_imm_6 has been removed
Register u2_ir_1 equivalent to u2_s4_1 has been removed
Register u2_ir_2 equivalent to u2_s4_2 has been removed
Register u2_ir_3 equivalent to u2_s4_3 has been removed
Register u2_ir_4 equivalent to u2_s4_4 has been removed
Register u2_ir_5 equivalent to u2_s4_5 has been removed
Register u2_ir_6 equivalent to u2_s4_6 has been removed
Register u2_ir_8 equivalent to u2_s5_0 has been removed
Register u2_ir_9 equivalent to u2_s5_1 has been removed
Register u2_ir_10 equivalent to u2_s5_2 has been removed
Register u2_ir_11 equivalent to u2_s5_3 has been removed
Register u2_ir_12 equivalent to u2_s5_4 has been removed
Register u2_ir_13 equivalent to u2_s5_5 has been removed
Register u2_ir_14 equivalent to u2_s5_6 has been removed
Found area constraint ratio of 100 (+ 5) on block cpu, actual ratio is 9.
FlipFlop u1_ex has been replicated 1 time(s)
FlipFlop u2_opcode_1 has been replicated 1 time(s)
FlipFlop u2_r1_0 has been replicated 2 time(s)
FlipFlop u2_r1_1 has been replicated 1 time(s)
FlipFlop u2_r1_2 has been replicated 1 time(s)
FlipFlop u2_opcode_3 has been replicated 1 time(s)
FlipFlop u2_opcode_2 has been replicated 1 time(s)
FlipFlop u2_opcode_0 has been replicated 1 time(s)
FlipFlop u1_ex has been replicated 1 time(s)
FlipFlop u1_ex has been replicated 1 time(s)
FlipFlop u2_s4_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s4_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u2_s5_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cpu.ngr
Top Level Output File Name         : cpu
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 97

Macro Statistics :
# Registers                        : 34
#      1-bit register              : 26
#      16-bit register             : 2
#      3-bit register              : 2
#      4-bit register              : 1
#      8-bit register              : 3
# Multiplexers                     : 54
#      2-to-1 multiplexer          : 52
#      8-bit 8-to-1 multiplexer    : 2
# Tristates                        : 3
#      16-bit tristate buffer      : 3
# Adders/Subtractors               : 2
#      15-bit adder                : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 456
#      GND                         : 1
#      LUT1                        : 16
#      LUT2                        : 21
#      LUT3                        : 120
#      LUT3_D                      : 1
#      LUT3_L                      : 32
#      LUT4                        : 172
#      LUT4_L                      : 1
#      MUXCY                       : 21
#      MUXF5                       : 32
#      MUXF6                       : 16
#      VCC                         : 1
#      XORCY                       : 22
# FlipFlops/Latches                : 240
#      FDC                         : 11
#      FDCE                        : 16
#      FDE                         : 75
#      FDP                         : 2
#      LD                          : 8
#      LD_1                        : 16
#      LDCP                        : 8
#      LDE                         : 104
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 96
#      IBUF                        : 1
#      IOBUF                       : 16
#      OBUF                        : 47
#      OBUFT                       : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                     208  out of   2352     8%  
 Number of Slice Flip Flops:           240  out of   4704     5%  
 Number of 4 input LUTs:               363  out of   4704     7%  
 Number of bonded IOBs:                 96  out of    170    56%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 104   |
u1_ex_3:Q                          | NONE                   | 53    |
u1_ex_2:Q                          | NONE                   | 51    |
u3__n0096(u3__n00961:O)            | NONE(*)(u3_mdrout_6)   | 24    |
u3_u1__n0002(u3_u1__n00021:O)      | NONE(*)(u3_u1_output_4)| 8     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 15.399ns (Maximum Frequency: 64.939MHz)
   Minimum input arrival time before clock: 13.192ns
   Maximum output required time after clock: 23.330ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               15.399ns (Levels of Logic = 6)
  Source:            u2_r1_0 (FF)
  Destination:       u2_pc_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u2_r1_0 to u2_pc_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             16   1.372   3.080  u2_r1_0 (u2_r1_0)
     LUT3_L:I0->LO         1   0.738   0.000  u3_Mmux__n0001_inst_lut3_121 (u3_Mmux__n0001__net7)
     MUXF5:I0->O           1   0.562   0.000  u3_Mmux__n0001_inst_mux_f5_2 (u3_Mmux__n0001__net9)
     MUXF6:I0->O           3   0.412   1.628  u3_Mmux__n0001_inst_mux_f6_1 (u3__n0001<1>)
     LUT4:I2->O            1   0.738   1.265  u2__n004115 (CHOICE223)
     LUT4_L:I1->LO         1   0.738   0.100  u2__n004161 (CHOICE235)
     LUT4:I0->O           16   0.738   3.080  u2__n0041132 (u2__n0041)
     FDCE:CE                   0.948          u2_pc_14
    ----------------------------------------
    Total                     15.399ns (6.246ns logic, 9.153ns route)
                                       (40.6% logic, 59.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_ex_2:Q'
Delay:               9.983ns (Levels of Logic = 5)
  Source:            u3_reg_0_5 (LATCH)
  Destination:       u3_input1_5 (LATCH)
  Source Clock:      u1_ex_2:Q falling
  Destination Clock: u1_ex_2:Q falling

  Data Path: u3_reg_0_5 to u3_input1_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              3   1.509   1.628  u3_reg_0_5 (u3_reg_0_5)
     LUT3_L:I1->LO         1   0.738   0.000  u3_Mmux__n0001_inst_lut3_281 (u3_Mmux__n0001__net35)
     MUXF5:I0->O           1   0.562   0.000  u3_Mmux__n0001_inst_mux_f5_10 (u3_Mmux__n0001__net37)
     MUXF6:I0->O           3   0.412   1.628  u3_Mmux__n0001_inst_mux_f6_5 (u3__n0001<5>)
     LUT4:I3->O            1   0.738   1.265  u3_Mmux__n0097_Result<5>15 (CHOICE189)
     LUT4:I1->O            1   0.738   0.000  u3_Mmux__n0097_Result<5>58 (u3__n0097<5>)
     LDE:D                     0.765          u3_input1_5
    ----------------------------------------
    Total                      9.983ns (5.462ns logic, 4.521ns route)
                                       (54.7% logic, 45.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_ex_3:Q'
Delay:               7.270ns (Levels of Logic = 2)
  Source:            u4_mdr1out_5 (LATCH)
  Destination:       u3_reg_7_5 (LATCH)
  Source Clock:      u1_ex_3:Q falling
  Destination Clock: u1_ex_3:Q falling

  Data Path: u4_mdr1out_5 to u3_reg_7_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.509   1.265  u4_mdr1out_5 (u4_mdr1out_5)
     LUT4:I3->O            8   0.738   2.255  u3_Ker91141 (u3_N9116)
     LUT4:I2->O            1   0.738   0.000  u3_Mmux__n0089_Result<5>1 (u3__n0089<5>)
     LDE:D                     0.765          u3_reg_7_5
    ----------------------------------------
    Total                      7.270ns (3.750ns logic, 3.520ns route)
                                       (51.6% logic, 48.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u3__n00961:O'
Delay:               4.486ns (Levels of Logic = 1)
  Source:            u3_mar_15 (LATCH)
  Destination:       u3_mar_15 (LATCH)
  Source Clock:      u3__n00961:O falling
  Destination Clock: u3__n00961:O falling

  Data Path: u3_mar_15 to u3_mar_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  u3_mar_15 (u3_mar_15)
     LUT3:I1->O            1   0.738   0.000  u3_Mmux__n0099_Result1 (u3__n0099)
     LDE:D                     0.765          u3_mar_15
    ----------------------------------------
    Total                      4.486ns (3.012ns logic, 1.474ns route)
                                       (67.1% logic, 32.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              13.192ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       u2_s4_7 (FF)
  Destination Clock: clk rising

  Data Path: rst to u2_s4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            32   0.989   4.180  rst_IBUF (rst_IBUF)
     LUT3:I2->O            2   0.738   1.474  u2_Ker80311 (u2_N8033)
     LUT3:I1->O           31   0.738   4.125  u2__n00041 (u2__n0004)
     FDE:CE                    0.948          u2_s5_1
    ----------------------------------------
    Total                     13.192ns (3.413ns logic, 9.779ns route)
                                       (25.9% logic, 74.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              23.330ns (Levels of Logic = 4)
  Source:            u1_t_1 (FF)
  Destination:       ABUS<15> (PAD)
  Source Clock:      clk rising

  Data Path: u1_t_1 to ABUS<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   1.372   2.145  u1_t_1 (u1_t_1)
     LUT3:I0->O           67   0.738   6.105  u3__n00871_1 (u3__n00871_1)
     LUT3:I2->O            2   0.738   1.474  u3_wr1 (wr2)
     LUT4:I3->O           32   0.738   4.180  u4__n00161 (u4__n0016)
     OBUFT:T->O                5.840          ABUS_0_OBUFT (ABUS<0>)
    ----------------------------------------
    Total                     23.330ns (9.426ns logic, 13.904ns route)
                                       (40.4% logic, 59.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u3__n00961:O'
Offset:              10.847ns (Levels of Logic = 2)
  Source:            u3_mar_15 (LATCH)
  Destination:       ABUS<15> (PAD)
  Source Clock:      u3__n00961:O falling

  Data Path: u3_mar_15 to ABUS<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  u3_mar_15 (u3_mar_15)
     LUT4:I2->O            2   0.738   1.474  u4_Mmux__n0006_Result<15>1 (ABUS_15_OBUFT)
     OBUFT:I->O                5.652          ABUS_15_OBUFT (ABUS<15>)
    ----------------------------------------
    Total                     10.847ns (7.899ns logic, 2.948ns route)
                                       (72.8% logic, 27.2% route)

=========================================================================
CPU : 7.00 / 7.39 s | Elapsed : 7.00 / 7.00 s
 
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Total memory usage is 65216 kilobytes