cpu.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: cpu.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : cpu.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : cpu
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : cpu
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : cpu.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu1/alu.vhd in Library work.
Architecture behavioral of Entity alu is up to date.
Compiling vhdl file F:/cpu1/timer.vhd in Library work.
Architecture behavioral of Entity timer is up to date.
Compiling vhdl file F:/cpu1/GetInstr.vhd in Library work.
Architecture behavioral of Entity getinstr is up to date.
Compiling vhdl file F:/cpu1/exe.vhd in Library work.
Architecture behavioral of Entity exe is up to date.
Compiling vhdl file F:/cpu1/memcontrol.vhd in Library work.
Architecture behavioral of Entity memcontrol is up to date.
Compiling vhdl file F:/cpu1/cpu.vhd in Library work.
Architecture behavioral of Entity cpu is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cpu> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/cpu1/cpu.vhd line 18: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - F:/cpu1/cpu.vhd line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <cpu> analyzed. Unit <cpu> generated.

Analyzing Entity <timer> (Architecture <behavioral>).
Entity <timer> analyzed. Unit <timer> generated.

Analyzing Entity <GetInstr> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <wr> in unit <GetInstr> never changes during circuit operation. The register is replaced by logic.
Entity <GetInstr> analyzed. Unit <GetInstr> generated.

Analyzing Entity <exe> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu1/exe.vhd line 52: The following signals are missing in the process sensitivity list:
   opcode, imm, output, mdrin<7>, mdrin<6>, mdrin<5>, mdrin<4>, mdrin<3>, mdrin<2>, mdrin<1>, mdrin<0>.
Entity <exe> analyzed. Unit <exe> generated.

Analyzing Entity <alu> (Architecture <behavioral>).
Entity <alu> analyzed. Unit <alu> generated.

Analyzing Entity <memcontrol> (Architecture <behavioral>).
WARNING:Xst:819 - F:/cpu1/memcontrol.vhd line 67: The following signals are missing in the process sensitivity list:
   ex.
Entity <memcontrol> analyzed. Unit <memcontrol> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alu>.
    Related source file is F:/cpu1/alu.vhd.
WARNING:Xst:737 - Found 8-bit latch for signal <output>.
    Found 8-bit addsub for signal <$n0007>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <alu> synthesized.


Synthesizing Unit <memcontrol>.
    Related source file is F:/cpu1/memcontrol.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <t> is never used.
WARNING:Xst:647 - Input <mdr0in> is never used.
WARNING:Xst:737 - Found 16-bit latch for signal <mdr0out>.
WARNING:Xst:737 - Found 16-bit latch for signal <mdr1out>.
    Found 16-bit tristate buffer for signal <DBUS>.
    Found 16-bit tristate buffer for signal <ABUS>.
    Found 16-bit tristate buffer for signal <s0>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  16 Multiplexer(s).
	inferred  48 Tristate(s).
Unit <memcontrol> synthesized.


Synthesizing Unit <exe>.
    Related source file is F:/cpu1/exe.vhd.
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <mdrin<15:8>> is never used.
WARNING:Xst:1305 - Output <mdrout<15:8>> is never assigned. Tied to value 00000000.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_0>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_7>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_6>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_5>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_4>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_3>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_2>.
WARNING:Xst:737 - Found 8-bit latch for signal <reg_1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input1>.
WARNING:Xst:737 - Found 8-bit latch for signal <input2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_15>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_14>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_13>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_12>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_11>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_10>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_9>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_8>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mar_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <mdrout_0>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0001> created at line 62.
    Found 8-bit 8-to-1 multiplexer for signal <$n0003> created at line 62.
    Found 104 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 120 Multiplexer(s).
Unit <exe> synthesized.


Synthesizing Unit <GetInstr>.
    Related source file is F:/cpu1/GetInstr.vhd.
WARNING:Xst:1305 - Output <mdrout> is never assigned. Tied to value 0000000000000000.
WARNING:Xst:646 - Signal <ir<0>> is assigned but never used.
    Found 16-bit register for signal <mar>.
    Found 3-bit register for signal <r1>.
    Found 3-bit register for signal <r2>.
    Found 8-bit register for signal <s4>.
    Found 8-bit register for signal <s5>.
    Found 1-bit register for signal <rd>.
    Found 8-bit register for signal <imm>.
    Found 4-bit register for signal <opcode>.
    Found 15-bit adder for signal <$n0025> created at line 42.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <pc>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  83 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred  16 Multiplexer(s).
Unit <GetInstr> synthesized.


Synthesizing Unit <timer>.
    Related source file is F:/cpu1/timer.vhd.
    Found finite state machine <FSM_0> for signal <q>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <ex>.
    Found 3-bit register for signal <t>.
    Found 1-bit register for signal <b0>.
    Found 1-bit register for signal <b1>.
    Found 1-bit register for signal <b2>.
    Found 1-bit register for signal <b3>.
    Found 1-bit register for signal <b4>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   6 D-type flip-flop(s).
Unit <timer> synthesized.


Synthesizing Unit <cpu>.
    Related source file is F:/cpu1/cpu.vhd.
Unit <cpu> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 32
  1-bit register                   : 23
  16-bit register                  : 2
  8-bit register                   : 3
  4-bit register                   : 1
  3-bit register                   : 3
# Latches                          : 37
  8-bit latch                      : 11
  16-bit latch                     : 2
  1-bit latch                      : 24
# Multiplexers                     : 54
  2-to-1 multiplexer               : 52
  8-bit 8-to-1 multiplexer         : 2
# Tristates                        : 3
  16-bit tristate buffer           : 3
# Adders/Subtractors               : 2
  8-bit addsub                     : 1
  15-bit adder                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <q> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <ir_0> is unconnected in block <GetInstr>.

Optimizing unit <cpu> ...

Optimizing unit <GetInstr> ...

Optimizing unit <timer> ...

Optimizing unit <alu> ...

Optimizing unit <exe> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.