getinstr.vhd

用VHDL 编写的一个16位的cpu 设计方案

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--******取指模块******

entity GetInstr is
port(
	clk,clr,rz,ex: in std_logic;
	t: in std_logic_vector(2 downto 0 );	  --高1位代表周期，低3位代表阶段
	r7:  in std_logic_vector(  7 downto 0 );
	s4,s5:out std_logic_vector(  7 downto 0 );	  --
	mar: out std_logic_vector( 15 downto 0 );	  --地址
	mdrin: in std_logic_vector( 15 downto 0 );
	mdrout:out std_logic_vector(15 downto 0);	  --数据
	rd,wr: out std_logic;			
	opcode :buffer std_logic_vector( 3 downto 0 );
	r1, r2 : out std_logic_vector( 2 downto 0 );
	imm :buffer std_logic_vector( 7 downto 0 )
	);
end GetInstr;

architecture Behavioral of GetInstr is

signal pc,ir:std_logic_vector( 15 downto 0 );
begin
	process(t,ex, clr,clk)
	variable num: integer:=0; 
	begin
	
	if clr = '1' then
		num := 0;	pc <=conv_std_logic_vector(0 , 16); rd<='0';wr<='0';
	elsif  clk='1' and clk'event then
		 rd<='0';wr<='0'; 
		if ex='0'then
		  case t is
			when "100" => mar <= pc;  rd <= '1';wr<='0';	   --第1周期的第1阶段
			when "010" => ir <= mdrin; s5<=mdrin(15 downto 8); s4<=mdrin(7 downto 0);
			              num:= conv_integer(pc);			   --第1周期的第2阶段
					    num:= num + 2;
					    pc <= conv_std_logic_vector(num, 16);
			when "001" => opcode <= ir(15 downto 12); --第1周期的第3阶段
						      r1 <= ir(11 downto 9);
						      r2 <= ir( 8 downto 6);
						      imm<= ir( 8 downto 1);
			when others=>NULL;
			end case;
	     elsif ex='1' and t="010"  and rz='1' then
						pc(7 downto 0)<=imm; 		--2周期的第1阶段,jz or jmp
						pc(15 downto 8)<=r7; 
		else NULL;
		end if;				
	  end if;
	end process;

end Behavioral;