getinstr.syr

用VHDL 编写的一个16位的cpu 设计方案

FlipFlop s4_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s4_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop s5_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : getinstr.ngr
Top Level Output File Name         : getinstr
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 99

Macro Statistics :
# Registers                        : 25
#      1-bit register              : 17
#      16-bit register             : 2
#      3-bit register              : 2
#      4-bit register              : 1
#      8-bit register              : 3
# Multiplexers                     : 16
#      2-to-1 multiplexer          : 16
# Adders/Subtractors               : 1
#      15-bit adder                : 1

Cell Usage :
# BELS                             : 68
#      GND                         : 1
#      LUT1_L                      : 15
#      LUT2                        : 2
#      LUT3                        : 5
#      LUT3_L                      : 14
#      LUT4                        : 2
#      MUXCY                       : 14
#      VCC                         : 1
#      XORCY                       : 14
# FlipFlops/Latches                : 79
#      FDC                         : 1
#      FDCE                        : 16
#      FDE                         : 62
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 82
#      IBUF                        : 30
#      OBUF                        : 52
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                      53  out of   2352     2%  
 Number of Slice Flip Flops:            79  out of   4704     1%  
 Number of 4 input LUTs:                38  out of   4704     0%  
 Number of bonded IOBs:                 82  out of    170    48%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 79    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.627ns (Maximum Frequency: 115.915MHz)
   Minimum input arrival time before clock: 12.422ns
   Maximum output required time after clock: 8.652ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               8.627ns (Levels of Logic = 17)
  Source:            pc_1 (FF)
  Destination:       pc_15 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: pc_1 to pc_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             3   1.372   1.628  pc_1 (pc_1)
     LUT1_L:I0->LO         1   0.738   0.000  Madd__n0025_inst_lut2_01 (Madd__n0025_inst_lut2_0)
     MUXCY:S->O            1   0.842   0.000  Madd__n0025_inst_cy_0 (Madd__n0025_inst_cy_0)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_1 (Madd__n0025_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_2 (Madd__n0025_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_3 (Madd__n0025_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_4 (Madd__n0025_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_5 (Madd__n0025_inst_cy_5)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_6 (Madd__n0025_inst_cy_6)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_7 (Madd__n0025_inst_cy_7)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_8 (Madd__n0025_inst_cy_8)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_9 (Madd__n0025_inst_cy_9)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_10 (Madd__n0025_inst_cy_10)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_11 (Madd__n0025_inst_cy_11)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0025_inst_cy_12 (Madd__n0025_inst_cy_12)
     MUXCY:CI->O           0   0.057   0.000  Madd__n0025_inst_cy_13 (Madd__n0025_inst_cy_13)
     XORCY:CI->O           1   0.538   1.265  Madd__n0025_inst_sum_14 (_n0001<15>)
     LUT3_L:I2->LO         1   0.738   0.000  Mmux__n0007_Result1 (_n0007)
     FDCE:D                    0.765          pc_15
    ----------------------------------------
    Total                      8.627ns (5.734ns logic, 2.893ns route)
                                       (66.5% logic, 33.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              12.422ns (Levels of Logic = 3)
  Source:            ex (PAD)
  Destination:       s4_7 (FF)
  Destination Clock: clk rising

  Data Path: ex to s4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   0.989   3.410  ex_IBUF (ex_IBUF)
     LUT3:I1->O            2   0.738   1.474  Ker12591 (N1261)
     LUT3:I0->O           31   0.738   4.125  _n00041 (_n0004)
     FDE:CE                    0.948          s5_1
    ----------------------------------------
    Total                     12.422ns (3.413ns logic, 9.009ns route)
                                       (27.5% logic, 72.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              8.652ns (Levels of Logic = 1)
  Source:            imm_7 (FF)
  Destination:       r2<2> (PAD)
  Source Clock:      clk rising

  Data Path: imm_7 to r2<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   1.372   1.628  imm_7 (imm_7)
     OBUF:I->O                 5.652          r2_2_OBUF (r2<2>)
    ----------------------------------------
    Total                      8.652ns (7.024ns logic, 1.628ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
CPU : 1.69 / 2.06 s | Elapsed : 2.00 / 2.00 s
 
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Total memory usage is 57024 kilobytes