getinstr.syr

用VHDL 编写的一个16位的cpu 设计方案

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: getinstr.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : getinstr.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : getinstr
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : getinstr
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : getinstr.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/cpu1/GetInstr.vhd in Library work.
Entity <getinstr> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <getinstr> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - F:/cpu1/GetInstr.vhd line 18: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - F:/cpu1/GetInstr.vhd line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1304 - Contents of register <wr> in unit <getinstr> never changes during circuit operation. The register is replaced by logic.
Entity <getinstr> analyzed. Unit <getinstr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <getinstr>.
    Related source file is F:/cpu1/GetInstr.vhd.
WARNING:Xst:1306 - Output <mdrout> is never assigned.
WARNING:Xst:646 - Signal <ir<0>> is assigned but never used.
    Found 8-bit register for signal <s4>.
    Found 8-bit register for signal <s5>.
    Found 16-bit register for signal <mar>.
    Found 1-bit register for signal <rd>.
    Found 4-bit register for signal <opcode>.
    Found 3-bit register for signal <r1>.
    Found 3-bit register for signal <r2>.
    Found 8-bit register for signal <imm>.
    Found 15-bit adder for signal <$n0025> created at line 42.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <pc>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  83 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred  16 Multiplexer(s).
Unit <getinstr> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 25
  1-bit register                   : 17
  16-bit register                  : 2
  8-bit register                   : 3
  4-bit register                   : 1
  3-bit register                   : 2
# Multiplexers                     : 16
  2-to-1 multiplexer               : 16
# Adders/Subtractors               : 1
  15-bit adder                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <ir_0> is unconnected in block <getinstr>.

Optimizing unit <getinstr> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register r2_2 equivalent to imm_7 has been removed
Register ir_7 equivalent to s4_7 has been removed
Register ir_15 equivalent to s5_7 has been removed
Register r2_0 equivalent to imm_5 has been removed
Register r2_1 equivalent to imm_6 has been removed
Register ir_1 equivalent to s4_1 has been removed
Register ir_2 equivalent to s4_2 has been removed
Register ir_3 equivalent to s4_3 has been removed
Register ir_4 equivalent to s4_4 has been removed
Register ir_5 equivalent to s4_5 has been removed
Register ir_6 equivalent to s4_6 has been removed
Register ir_8 equivalent to s5_0 has been removed
Register ir_9 equivalent to s5_1 has been removed
Register ir_10 equivalent to s5_2 has been removed
Register ir_11 equivalent to s5_3 has been removed
Register ir_12 equivalent to s5_4 has been removed
Register ir_13 equivalent to s5_5 has been removed
Register ir_14 equivalent to s5_6 has been removed
Found area constraint ratio of 100 (+ 5) on block getinstr, actual ratio is 1.