exemplar.log

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。

LeonardoSpectrum Level 3 - v20001b.106 (Release Production, compiled Dec  4 2000 at 17:05:11)
Copyright 1990-2000 Exemplar Logic, Inc.  All rights reserved.

--
-- Welcome to LeonardoSpectrum Level 3
-- Run By Administrator@7722D82C563240C
-- Run Started On Sat Jul 01 10:00:08 中国标准时间 2006
--
Info, Working Directory is now 'E:\assignment\Verilog\task\assignment\spc'
50
50
50
50
 E:/assignment/Verilog/task/assignment/spc/spc.v 
2s15cs144
5
xis215-5_avg
FALSE
FALSE
brief
TRUE
FALSE
E:/assignment/Verilog/task/test/news5f/spc.edf
FALSE
xis2
-- Reading target technology xis2
Reading library file `d:\Exemplar\LeoSpec\v20001b\lib\xis2.syn`...
Library version = 3.500000
Delays assume: Process=5 
-- read -tech xis2 { E:/assignment/Verilog/task/assignment/spc/spc.v }
-- Reading file 'E:/assignment/Verilog/task/assignment/spc/spc.v'...
-- Loading module iospc
-- Compiling root module 'iospc'
-- Pre Optimizing Design .work.iospc.INTERFACE
-- Boundary optimization.
"E:/assignment/Verilog/task/assignment/spc/spc.v", line 26:Info, Inferred counter instance 'count_s_out' of type 'counter_up_sclear_aclear_clock_clk_en_4'
Info: Finished reading design
-- Run Started On Sat Jul 01 10:01:11 中国标准时间 2006
--
-- optimize -target xis2 -effort quick -chip -area -hierarchy=auto
Using wire table: xis215-5_avg
-- Start optimization for design .work.iospc.INTERFACE
Using wire table: xis215-5_avg
                                                            
      Pass     Area    Delay      DFFs   PIs   POs   --CPU--
              (LUTs)    (ns)                         min:sec
      1         16       11        14     3     9     00:00 
Info, Added global buffer BUFGP for port clk 
Using wire table: xis215-5_avg
-- Start timing optimization for design .work.iospc.INTERFACE
No critical paths to optimize at this level

*******************************************************

Cell: iospc    View: INTERFACE    Library: work

*******************************************************

 Number of ports :                      12
 Number of nets :                       57
 Number of instances :                  45
 Number of references to this view :     0

Total accumulated area : 
 Number of BUFGP :                       1
 Number of Dffs or Latches :            14
 Number of Function Generators :        19
 Number of IBUF :                        2
 Number of IOBUF :                       9

***********************************************
Device Utilization for 2s15cs144
***********************************************
Resource                Used    Avail   Utilization
-----------------------------------------------
IOs                     12      86       13.95%
Function Generators     19      384       4.95%
CLB Slices              10      192       5.21%
Dffs or Latches         14      672       2.08%

-----------------------------------------------
                        Clock Frequency Report

	Clock                : Frequency
      ------------------------------------

	clk                  : 124.5 MHz

                        Critical Path Report


Critical path #1, (path slack = 38.7):

NAME                                 GATE              ARRIVAL              LOAD
--------------------------------------------------------------------------------
sp/                                              0.00  0.00 up             1.90
sp_ibuf/O                            IBUF        2.92  2.92 up             3.70
NOT_sp/O                             LUT1        2.39  5.31 up             3.30
p_inout(0)_bdbuf/IO                  IOBUF       6.00  11.31 up             1.90
p_inout(0)/                                      0.00  11.31 up             0.00
data arrival time                                      11.31

data required time  (default specified)                50.00
--------------------------------------------------------------------------------
data required time                                     50.00
data arrival time                                      11.31
                                                    ----------
slack                                                 38.69
--------------------------------------------------------------------------------




-- Design summary in file 'E:/assignment/Verilog/task/test/news5f/spc.sum'
-- Saving the design database in E:/assignment/Verilog/task/test/news5f/spc.xdb
-- Writing file E:/assignment/Verilog/task/test/news5f/spc.xdb
-- Writing XDB version 1999.1
-- Writing file E:/assignment/Verilog/task/test/news5f/spc.edf
Info, Writing NCF file 'E:/assignment/Verilog/task/test/news5f/spc.ncf'
-- Writing file E:/assignment/Verilog/task/test/news5f/spc.ncf
-- CPU time taken for this run was  2.1 sec
-- Run Successfully Ended On  Sat Jul 01 10:01:14 中国标准时间 2006
0
Info: Finished Synthesis run