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📄 fsm_temp.sum

📁 Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。
💻 SUM
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*******************************************************

Cell: CODETEST    View: INTERFACE    Library: work

*******************************************************

Total accumulated area : 
 Number of BUFGP :                       1
 Number of Dffs or Latches :             4
 Number of Function Generators :         8
 Number of IBUF :                        2
 Number of MUXF5 :                       1
 Number of OBUF :                        1

 Number of ports :                       4
 Number of nets :                       21
 Number of instances :                  18
 Number of references to this view :     0


             Cell          Library  References     Total Area

            BUFGP             xis2     1 x      1      1 BUFGP
              FDC             xis2     2 x      1      2 Dffs or Latches
             FDCE             xis2     1 x      1      1 Dffs or Latches
              GND             xis2     1 x      1      1 GND
             IBUF             xis2     2 x      1      2 IBUF
               LD             xis2     1 x      1      1 Dffs or Latches
             LUT1             xis2     1 x      1      1 Function Generators
             LUT3             xis2     2 x      1      2 Function Generators
             LUT4             xis2     5 x      1      5 Function Generators
            MUXF5             xis2     1 x      1      1 MUXF5
             OBUF             xis2     1 x      1      1 OBUF

***********************************************
Device Utilization for 2s15cs144
***********************************************
Resource                Used    Avail   Utilization
-----------------------------------------------
IOs                     4       86        4.65%
Function Generators     8       384       2.08%
CLB Slices              4       192       2.08%
Dffs or Latches         4       672       0.60%

-----------------------------------------------
Using wire table: xis215-5_avg



                        Clock Frequency Report

	Clock                : Frequency
      ------------------------------------

	clk                  : 180.5 MHz
	rst                  : 193.8 MHz

                        Slack Table at End Points


End points                         Slack       Arrival             Required
                                             rise     fall      rise     fall

Z/                             :   38.18      11.82   11.82      50.00   50.00   
reg_state(2)/CE                :   44.46      4.64   4.64      49.10   49.10   
reg_state(2)/D                 :   44.84      4.64   4.64      49.48   49.48   
lat_Z_mark/D                   :   44.84      4.64   4.64      49.48   49.48   
reg_state(0)/D                 :   44.84      4.64   4.64      49.48   49.48   
reg_state(1)/D                 :   44.84      4.64   4.64      49.48   49.48   
lat_Z_mark/G                   :   45.36      4.64   4.64      50.00   50.00   
reg_state(1)/CLR               :   45.89      4.11   4.11      50.00   50.00   
reg_state(2)/CLR               :   45.89      4.11   4.11      50.00   50.00   
reg_state(0)/CLR               :   45.89      4.11   4.11      50.00   50.00   



                        Critical Path Report


Critical path #1, (path slack = 38.2):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(1)/Q                     FDC         0.00  2.95 up             3.10
nx207/O                            LUT4        1.69  4.64 up             1.90
ix208/O                            MUXF5       1.35  5.99 up             1.90
Z_obuf/O                           OBUF        5.83  11.82 up             1.90
Z/                                             0.00  11.82 up             0.00
data arrival time                                    11.82

data required time  (default specified)              50.00
------------------------------------------------------------------------------
data required time                                   50.00
data arrival time                                    11.82
                                                  ----------
slack                                               38.18
------------------------------------------------------------------------------




Critical path #2, (path slack = 38.3):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(2)/Q                     FDCE        0.00  2.85 up             2.90
nx207/O                            LUT4        1.69  4.54 up             1.90
ix208/O                            MUXF5       1.35  5.89 up             1.90
Z_obuf/O                           OBUF        5.83  11.72 up             1.90
Z/                                             0.00  11.72 up             0.00
data arrival time                                    11.72

data required time  (default specified)              50.00
------------------------------------------------------------------------------
data required time                                   50.00
data arrival time                                    11.72
                                                  ----------
slack                                               38.28
------------------------------------------------------------------------------




Critical path #3, (path slack = 38.9):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
rst/                                           0.00  0.00 up             1.90
rst_ibuf/O                         IBUF        2.22  2.22 up             2.30
nx207/O                            LUT4        1.69  3.91 up             1.90
ix208/O                            MUXF5       1.35  5.26 up             1.90
Z_obuf/O                           OBUF        5.83  11.09 up             1.90
Z/                                             0.00  11.09 up             0.00
data arrival time                                    11.09

data required time  (default specified)              50.00
------------------------------------------------------------------------------
data required time                                   50.00
data arrival time                                    11.09
                                                  ----------
slack                                               38.91
------------------------------------------------------------------------------




Critical path #4, (path slack = 39.5):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


lat_Z_mark/Q                       LD          0.00  1.65 up             1.90
nx207/O                            LUT4        1.69  3.34 up             1.90
ix208/O                            MUXF5       1.35  4.69 up             1.90
Z_obuf/O                           OBUF        5.83  10.52 up             1.90
Z/                                             0.00  10.52 up             0.00
data arrival time                                    10.52

data required time  (default specified)              50.00
------------------------------------------------------------------------------
data required time                                   50.00
data arrival time                                    10.52
                                                  ----------
slack                                               39.48
------------------------------------------------------------------------------




Critical path #5, (path slack = 39.9):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(0)/Q                     FDC         0.00  2.85 up             2.90
ix208/O                            MUXF5       1.45  4.30 up             1.90
Z_obuf/O                           OBUF        5.83  10.13 up             1.90
Z/                                             0.00  10.13 up             0.00
data arrival time                                    10.13

data required time  (default specified)              50.00
------------------------------------------------------------------------------
data required time                                   50.00
data arrival time                                    10.13
                                                  ----------
slack                                               39.87
------------------------------------------------------------------------------




Critical path #6, (path slack = 44.5):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(1)/Q                     FDC         0.00  2.95 up             3.10
nx205/O                            LUT3        1.69  4.64 up             1.90
reg_state(2)/CE                    FDCE        0.00  4.64 up             0.00
data arrival time                                    4.64


data required time  (default specified - setup time)   49.10
------------------------------------------------------------------------------
data required time                                   49.10
data arrival time                                    4.64
                                                  ----------
slack                                               44.46
------------------------------------------------------------------------------




Critical path #7, (path slack = 44.6):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(0)/Q                     FDC         0.00  2.85 up             2.90
nx205/O                            LUT3        1.69  4.54 up             1.90
reg_state(2)/CE                    FDCE        0.00  4.54 up             0.00
data arrival time                                    4.54


data required time  (default specified - setup time)   49.10
------------------------------------------------------------------------------
data required time                                   49.10
data arrival time                                    4.54
                                                  ----------
slack                                               44.56
------------------------------------------------------------------------------




Critical path #8, (path slack = 44.8):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(1)/Q                     FDC         0.00  2.95 up             3.10
nextstate(1)/O                     LUT4        1.69  4.64 up             1.90
reg_state(1)/D                     FDC         0.00  4.64 up             0.00
data arrival time                                    4.64


data required time  (default specified - setup time)   49.48
------------------------------------------------------------------------------
data required time                                   49.48
data arrival time                                    4.64
                                                  ----------
slack                                               44.84
------------------------------------------------------------------------------




Critical path #9, (path slack = 44.8):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(1)/Q                     FDC         0.00  2.95 up             3.10
nextstate(0)/O                     LUT4        1.69  4.64 up             1.90
reg_state(0)/D                     FDC         0.00  4.64 up             0.00
data arrival time                                    4.64


data required time  (default specified - setup time)   49.48
------------------------------------------------------------------------------
data required time                                   49.48
data arrival time                                    4.64
                                                  ----------
slack                                               44.84
------------------------------------------------------------------------------




Critical path #10, (path slack = 44.8):

NAME                               GATE              ARRIVAL              LOAD
------------------------------------------------------------------------------
clock information not specified
delay thru clock network                             0.00 (ideal)


reg_state(1)/Q                     FDC         0.00  2.95 up             3.10
nx115/O                            LUT4        1.69  4.64 up             1.90
lat_Z_mark/D                       LD          0.00  4.64 up             0.00
data arrival time                                    4.64


data required time  (default specified - setup time)   49.48
------------------------------------------------------------------------------
data required time                                   49.48
data arrival time                                    4.64
                                                  ----------
slack                                               44.84
------------------------------------------------------------------------------


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