fa.txt

实现四位加法器的VHDL代码

library ieee;
use ieee.std_logic_1164.all;

entity fa is
    port(a,b,cin : in std_logic;
            s,cout : out std_logic);
end fa;

architecture b_fa of fa is
begin
    s<=a xor b xor cin;
    cout<=((a xor b) and cin) or (a and b);
end b_fa;