tb_comparator.vhd

这个是Xilinx编程的源码

--------------------------------------
--  entity       = tb_comparator    --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
--------------------------------------


-- test bench for comparator

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_textio.all;
use std.textio.all;


entity tb_comparator is
end tb_comparator;

architecture tb of tb_comparator is


component comparator 
   port (
	  indata_a : in std_logic_vector(3 downto 0);
	  indata_b : in std_logic_vector(3 downto 0); 
	  lt : out std_logic; 
	  eq : out std_logic   	  
    );
end component; 


signal indata_a : std_logic_vector(3 downto 0);
signal indata_b : std_logic_vector(3 downto 0);
signal lt : std_logic;
signal eq : std_logic;

begin


-- instantiate the device under test
dut : component comparator 
   port map(
	  indata_a => indata_a,
	  indata_b => indata_b, 
	  lt => lt, 
	  eq => eq  	  
    ); 

test : process


begin


	indata_a <= (others => '0');
	
	indata_b <= (others => '0');

	wait for (100 ns);

	indata_a <= "0010";
	
	indata_b <= "0001";

	wait for (100 ns);

	indata_a <= "0010";
	
	indata_b <= "0011";

	wait for (100 ns);

	indata_a <= "0100";
	
	indata_b <= "0100";

	wait for (100 ns);

	indata_a <= "0101";
	
	indata_b <= "0100";

            

end process test;



end tb; --end of architecture