reg_file.vhd.bak

这个是Xilinx编程的源码

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--  entity       = register file   --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
--------------------------------------

-- register file stores 5 numbers


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity register_file is
port
(
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	srd : in std_logic_vector(2 downto 0);
	enwr : in std_logic;
	swr : in std_logic_vector(2 downto 0);
	clear : in std_logic; -- general asyncronous reset
	reset : in std_logic; --general syncronous reset
	new_sort : in std_logic; -- start sorting new numbers
	data_middle  : out std_logic_vector(3 downto 0);
	data_out : out std_logic_vector(3 downto 0)
);

end register_file;

architecture struct of register_file is

-- one 4-bit register

component register4
port
(	
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	enwr : in std_logic;
	reset : in std_logic;
	new_sort : in std_logic;
	clear : in std_logic;
	data_out : out std_logic_vector(3 downto 0)
);
end component;

type type_reg_file is array(4 downto 0) of std_logic_vector(3 downto 0);
signal data_out_reg : type_reg_file;
signal enwr_reg : std_logic_vector(4 downto 0);

begin

data_middle <= data_out_reg(2); -- middle value

-- generate the registers

reg_array : for i in 0 to 4 generate
    	
    	regs : register4 port map ( 
    		clk => clk,
    		data_in => data_in,
    		enwr => enwr_reg(i),
    		reset => reset,
    		clear => clear,
    		new_sort => new_sort,
    		data_out => data_out_reg(i));

    	
end generate;  
  
  

read_reg : process (srd,data_out_reg)  -- read control
begin
	case srd is
		when "000" =>
			data_out <= data_out_reg(0);
		when "001" =>
			data_out <= data_out_reg(1);
		when "010" =>
			data_out <= data_out_reg(2);
		when "011" =>
			data_out <= data_out_reg(3);
		when "100" =>
			data_out <= data_out_reg(4);
		when others => null;	
	end case;

end process read_reg;


write_reg : process (swr,enwr)  -- write control
begin
	if (enwr = '1') then
		case swr is
			when "000" =>
				enwr_reg <= "00001";
			when "001" =>
				enwr_reg <= "00010";
			when "010" =>
				enwr_reg <= "00100";
			when "011" =>
				enwr_reg <= "01000";
			when "100" =>
				enwr_reg <= "10000";
			when others => null;	
		end case;
	else
		enwr_reg <= "00000";
	end if;
	
end process write_reg;



end struct;  -- end of architecture