register4.vhd

来自「这个是Xilinx编程的源码」· VHDL 代码 · 共 41 行

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--  entity       = register4        --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
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-- 4 bit register for register file

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity register4 is
port
(	
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	enwr : in std_logic;
	reset : in std_logic;
	clear : in std_logic;
	new_sort : in std_logic;
	data_out : out std_logic_vector(3 downto 0)
);
end register4;

architecture struct of register4 is
    
-- add signals here
    
begin

-- add code here

end struct;  -- end of architecture