tb_sorter.vhd.bak

这个是Xilinx编程的源码

--------------------------------------
--  entity       = tb_sorter        --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
--------------------------------------


-- test bench for sorter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_textio.all;
use std.textio.all;


entity tb_sorter is
end tb_sorter;

architecture tb of tb_sorter is


component sorter 
port 
(	
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	nrdy : in std_logic;
	reset : in std_logic;
	clear : in std_logic;
	nack : out std_logic;
	data_middle : out std_logic_vector(3 downto 0)
);
end component;


signal clk : std_logic;
signal reset : std_logic;
signal clear : std_logic;
signal data_in : std_logic_vector(3 downto 0);
signal data_middle  : std_logic_vector(3 downto 0);
signal nack : std_logic;
signal nrdy : std_logic;


-- procedures to test for wrong outputs

--********************************************************************
procedure print_sig_val_data(expected_data: std_logic_vector;received_data: std_logic_vector)  is
  variable tranx : line;
 -- variable l : line;
--********************************************************************  
begin
   
   --print to output screen

   write(tranx, now, justified=>right,field =>10, unit=> ns );
   write(tranx, string'(" Error in  data middle out   Expected: "));
   hwrite(tranx, expected_data);
   write(tranx, string'("   Received: "));
   hwrite(tranx, received_data);
   writeline(output,tranx);
end print_sig_val_data;     

--********************************************************************
procedure print_sig_val_nack(expected_data: std_logic;received_data: std_logic)  is
  variable tranx : line;
 -- variable l : line;
--********************************************************************  

begin
   
   --print to output screen
   write(tranx, now, justified=>right,field =>10, unit=> ns );
   write(tranx, string'(" Error in nack Expected: "));
   write(tranx,expected_data);
   write(tranx, string'("   Received: "));
   write(tranx,received_data);
   writeline(output,tranx);
end print_sig_val_nack;     


--  set up constants for test vector application & monitoring

constant clock_period: time := 100 ns;
constant half_period : time := clock_period / 2;
constant strobe_time : time := 0.9 * half_period;

begin


-- instantiate the device under test
dut : sorter 
port map
(	
	clk =>clk,
	data_in =>data_in,
	nrdy =>nrdy,
	reset =>reset,
	clear =>clear,
	nack =>nack,
	data_middle => data_middle 
);

 
test : process

file tv_in : text open read_mode is "sorter_in.dat";	-- test vectors

variable lin : line; -- temp variables			                          
variable i_data_in: std_logic_vector(3 downto 0) := (others => '0');
variable i_nrdy: std_logic := '1';
variable i_reset : std_logic := '0';
variable o_nack : std_logic;
variable o_data_middle : std_logic_vector(3 downto 0);
variable e_nack : std_logic;
variable e_data_middle : std_logic_vector(3 downto 0);

variable space : character;


begin

	-- clear and reset

	data_in <= (others => '0');
	
	nrdy <= '1';
  
	clear <= '1';

	reset <= '1';

	clk <= '1';  	-- rising clock edge

	wait for (half_period);

	clk <= '0';  	

	wait for (half_period);
	
	clear <= '0';

	clk <= '1';  	-- rising clock edge

	wait for (half_period);

	clk <= '0';  	

	wait for (half_period);

  	clear <= '0';

	reset <= '0';

   	clk <= '1';  	-- rising clock edge

	wait for (half_period);

	clk <= '0';  	

	wait for (half_period);
	
   	clk <= '1';  	-- rising clock edge

	wait for (half_period);

	clk <= '0';  	

	wait for (half_period);
	
	-- start applying test vectors
  
  while not(endfile(tv_in)) loop				-- check for end of file

  	readline(tv_in , lin);
  	read(lin, i_reset);
  	read(lin, space);
  	read(lin , i_data_in);
	read(lin, space);
	read(lin , i_nrdy);
	read(lin, space);
	read(lin , e_data_middle);
	read(lin, space);
	read(lin , e_nack);
				
	clk <= '1';					-- rising clock edge

        wait for 2 ns;

	reset <= i_reset;
	data_in <= i_data_in;
 	nrdy <= i_nrdy; -- apply input
	
	wait for (half_period - 2 ns);
	
	
	clk <= '0';		
	
	wait for strobe_time;				-- wait for strobe time
	
    	o_data_middle := data_middle;

	o_nack := nack;
	
	
	-- compare actual circuit response with expected response vectors
	if (e_data_middle /= o_data_middle) then
     		print_sig_val_data(e_data_middle,o_data_middle);
			report "Unexpected value in output data middle." severity error;
	end if;
	
	
 	if (e_nack /= o_nack) then
 		print_sig_val_nack(e_nack,o_nack);
		report "Unexpected value in output nack." severity error;  	
	end if;


 	wait for (half_period - strobe_time);		-- resynchronise with tester period

end loop;

-- this is not a failure only a way to stop the simulator

assert false
           report "END OF FILE ENCOUNTERED" severity FAILURE;
            

end process test;



end tb; --end of architecture