lab3.vhd.bak

16位的移位寄存器

library ieee ;
use ieee.std_logic_1164.all;

entity shift_register is 
    port(Clk,Rst,Enable: in std_logic;
         Data_in: in std_logic_vector(7 downto 0);
         Addr: in std_logic_vector(3 downto 0);
         Data_out: out std_logic_vector(7 downto 0));
end shift_register;

Architecture shift_register1 of shift_register is 
type reg_array is array (15 downto 0) of std_logic_vector (7 downto 0);
signal reg: reg_array;

begin

  regist: process(Rst,Clk,Enable)
   -- variable  reg: reg_array;
               
   begin
        if Rst= '1' then
         for i in 0 to 15 loop
            reg(i) <= "00000000";
            end loop;
         elsif rising_edge(Clk) then
           if Enable = '1' then
              reg(0) <= Data_in ;
              reg(15 downto 1) <= reg(14 downto 0);
            else
              reg(15 downto 0) <= reg(15 downto 0);
           end if;
         end if;
      If Addr <= "0000" then
      Data_out <= reg(0);
       elsif Addr <= "0001" then
      Data_out <= reg(1);
       elsif Addr <= "0010" then
      Data_out <= reg(2);
       elsif Addr <= "0011" then
      Data_out <= reg(3);
       elsif Addr <= "0100" then
      Data_out <= reg(4);
       elsif Addr <= "0101" then
      Data_out <= reg(5);
       elsif Addr <= "0110" then
      Data_out <= reg(6);
       elsif Addr <= "0111" then
      Data_out <= reg(7);
       elsif Addr <= "1000" then
      Data_out <= reg(8);
       elsif Addr <= "1001" then
      Data_out <= reg(9);
       elsif Addr <= "1010" then
      Data_out <= reg(10);
       elsif Addr <= "1011" then
      Data_out <= reg(11);
       elsif Addr <= "1100" then
      Data_out <= reg(12);
       elsif Addr <= "1101" then
      Data_out <= reg(13);
       elsif Addr <= "1110" then
      Data_out <= reg(14);
       elsif Addr <= "1111" then
      Data_out <= reg(15);
      end if ;
          
   end process;
end shift_register1 ;