testbench.v

来自「硬件描述语言,verilog HDL,实现了解码器的设计」· Verilog 代码 · 共 51 行

module testbentch;

	5reg  bit_in,reset,clk;
	wire en,out,v;
	parameter size=13,period=10;
	integer addr=0;

	reg mem[0:size]; 

	integer fid; 
	golomb2 golomb1(bit_in,clk,reset,en,out,v);
      initial mem[0]=1'b1;
            initial
             begin
                       clk=0;
                       forever
                               #(period/2)  clk=~clk;
               end
            initial
   begin
       reset=1;
       #period reset=0;
       
   end
           
			
                 
initial $readmemb("/home/liang1205/ldv/shifeng/code.txt",mem,1);

always @(posedge clk)
begin
    if(en)
	begin
	 addr=addr+1;
	end
    bit_in=mem[addr];
    if(addr==size) $finish;    
end

initial fid=$fopen("decode.txt");

always @(posedge clk)
begin
    if(v)
    $fwrite(fid,"%b",out);
end



endmodule