golomb2.v

硬件描述语言,verilog HDL,实现了解码器的设计

module golomb2(clk,reset,bit_in,out,en,v);
input  clk,reset,bit_in;
output  out,en,v;
reg  out,en,v;
reg[3:0]  state,next_state;

parameter  s1=4'b0001,
          s2=4'b0010, s3=4'b0011,
          s4=4'b0100, s5=4'b0101,
          s6=4'b0110, s7=4'b0111,
          s8=4'b1000, s9=4'b1001,
          s10=4'b1010;
always @(posedge clk or posedge reset)
begin 
    if(reset) state<=s0;
    else state<=next_state;
end

always @(state or bit_in)
begin
case(state)
   
   s1: begin
        en=(bit_in)?0:1;
        out=(bit_in)?0:1;
        v=(bit_in)?1:0;
        next_state<=(bit_in)?s2:s6;
       end  
   s2: begin
        en=0;
        out=0;
        v=1;
        next_state<=s3;
       end
   s3: begin
        en=0;
        out=0;
        v=1;
        next_state<=s4;
       end
   s4: begin
        en=1;
        out=0;
        v=1;
        next_state<=s5;
       end
   s5: begin
        en=(bit_in)?0:1;
        out=(bit_in)?0:1;
        v=(bit_in)?1:0;
        next_state<=(bit_in)?s2:s6;
       end
   s6: begin
        en=1;
        out=(bit_in)?0:1;
        v=(bit_in)?1:0;
        next_state<=(bit_in)?s8:s7;
       end
   s7: begin
        en=0;
        out=(bit_in)?0:1;
        v=(bit_in)?1:0;
        next_state<=s10;
       end
   s8: begin 
        en=0;
        out=0;
        v=1;
        next_state<=(bit_in)?s9:s10;
       end
   s9: begin
        en=0;
        out=0;
        v=1;
        next_state<=s10;
       end
   s10: begin
        en=1;
        out=1;
        v=1;
        next_state<=s1;
       end

    default: begin
             en=1;
             out=1;
             v=0;
            next_state<=s1;
            end
endcase
end

endmodule