adma_defines.v

Wishbone dma ip core

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////  Design definitions of ADMA IP Core                          ////
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////  This file is part of the ADMA project                       ////
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////  Description                                                 ////
////  Design definitions.                                         ////
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////  To Do:                                                      ////
////   Nothing                                                    ////
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////  Author(s):                                                  ////
////      - Damjan Lampret, [e-mail]                 ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// later version.                                               ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
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//
// CVS Revision History
//
// $Log: adma_defines.v,v $
// Revision 1.1.1.1  2002/08/13 03:12:41  lampret
// First import.
//
//
//

//
// ADMA is a simple WISHBONE DMA, that was designed to be very small
// (Area optimized). ADMA can mainly be used in two scenarios:
// 1) With a slave peripheral IP core to add DMA capability to
//    the peripheral. This way several small peripheral IP cores can
//    be extend with DMA functionality, w/o designing new DMA function
//    for every peripheral core.
// 2) To add DMA functionality into a small system-on-chip (eg. between
//    peripherals, peripherals and memory, or between memories), possibly
//    SoC implemented on an FPGA where resources are sometimes limited.
//    ADMA is very small, however powerful enough for most applications.
//
// For reasons mentioned ADMA is designed w/o registered outputs. It is advised
// that all control output signals from ADMA should first be sampled before
// using them.
//
// Description of ADMA WISHBONE interfaces (from ADMA
// point of view):
// - host interface: WISHBONE slave interface
//   (normally connected to the CPU and used that CPU
//   can program ADMA registers, or make accesses onto
//   peripheral interface)
// - system interface: WISHBONE master interface
//   (normally connected to memory and rest of the system.
//   DMA descriptors, if implemented, can only be loaded
//   via system interface)
// - peripheral interface: WISHBONE master interface +
//   slave DMA Req/Ack/ND signals
//   (normally connected to a peripheral, or to another ADMA.
//   Peripheral interface has DMA Req/Ack signals, can
//   be destination for accesses coming from host interface and can't
//   be used for loading DMA descriptors nor for random memory accesses)
//
// ADMA can be programmed by the host for every new DMA transfer (DMA transfer
// is a several WISHBONE system/peripheral accesses). Number of WISHBONE
// accesses is programmed into LDR, where value represents value+1 acceses.
// After every DMA transfer, an interrupt can be asserted.
// If an error happens, error interrupt can be aserted. If interrupts are
// not enabled (CR[EN_ERRINT], CR[EN_DONEINT), status of DMA transfer can
// be seen in configuration register (CR[DONE], CR[ERR]).
//
// If DMA descriptors are implemented and enabled, host processor doesn't have
// to worry to set up every new DMA transfer. Instead a chain of descriptors
// describing DMA transfers can be set up in memory (only accessible by system
// interface). To use descriptors, pointer to first descriptor must be placed
// into DPR and fetch of descriptors must be enabled with CR[FD].
//
// If ADMA is used to transfer data from a constant source or to a constant
// destination address (eg. peripheral's register), clear CR[INC_AIR] to
// prevent address increment.
//
// If ADMA is used w/o peripheral interface's DMA Req/Ack signals, for example
// to transfer data from memory area to a different memory area, enable
// so called "software mode" by setting CR[SM].
// To implement memory-to-memory transfers, you need to use two ADMA's linked
// together by their peripheral interfaces. DMA Req/Ack from one ADMA should
// be swapped and connected to second ADMA's DMA Ack/Req signals. This is
// needed because every ADMA implements only a single address register (AIR)
// that can only address memory via system interface. To implement both
// source and destination address pointers, two ADMAs linked together are
// needed.
//
// ADMA register map (on 32-bit system):
// Base + 0x0: Length decrement register
// Base + 0x4: Control register
// Base + 0x8: Address increment register
// Base + 0xc: Descriptor pointer register
//
// ADMA descriptor in memory (32-bit system):
// Base + 0x0: DMA transfer length
// Base + 0x4: Control bits (same as control register CR)
// Base + 0x8: Start address
// Base + 0xc: Next descriptor pointer
//

//
// ADMA implementation
//
// If defined, ADMA is implemented.
//
// If not defined, ADMA is not implemented
// and ADMA's WISHBONE host and WISHBONE peripheral
// interface are permanently connected.
// System interface is disabled.
// 
`define ADMA_IMPLEMENTED

//
// Implementation of descriptors
//
// If not defined, DPR and descriptor fetching
// are not implemented.
//
`define ADMA_DESCRIPTORS 

//
// Length of maximum DMA transfer (number of WISHBONE transfers)
//
// Number of WISHBONE transfers is determined by calculating 2^MAXLEN
//
`define ADMA_MAXLEN 12

//////////////////////////////////////////////////////////////////////////////
//
// DO NOT MODIFY BELOW THIS LINE
//

//
// Offsets of ADMA registers
//
// Don't change or test bench will fail (due to descriptors in memory).
//
`define ADMA_OFS_LDR 2'h0
`define ADMA_OFS_CR 2'h1
`define ADMA_OFS_AIR 2'h2
`define ADMA_OFS_DPR 2'h3
`define ADMA_OFS 3:2
`define ADMA_BASE 31:28
`define ADMA_MATCH_DMA_BASE h_adr_i[`ADMA_BASE] == base_dma
`define ADMA_MATCH_LDR h_adr_i[`ADMA_OFS] == `ADMA_OFS_LDR
`define ADMA_MATCH_CR h_adr_i[`ADMA_OFS] == `ADMA_OFS_CR
`define ADMA_MATCH_DPR h_adr_i[`ADMA_OFS] == `ADMA_OFS_DPR
`define ADMA_MATCH_AIR h_adr_i[`ADMA_OFS] == `ADMA_OFS_AIR

//
// Control register bits
//
// Don't change or test bench will fail (due to descriptors in memory).
//
`define ADMA_CR_EN 0
`define ADMA_CR_WM 1
`define ADMA_CR_INC_AIR 2
`define ADMA_CR_DONE 3
`define ADMA_CR_ERR 4
`define ADMA_CR_EN_DONEINT 5
`define ADMA_CR_EN_ERRINT 6
`define ADMA_CR_SM 7
`define ADMA_CR_FD 8

//
// Fetch descriptors FSM states
//
`define ADMA_FDFSM_IDLE 3'd0
`define ADMA_FDFSM_LENGTH 3'd1
`define ADMA_FDFSM_CTRL 3'd2
`define ADMA_FDFSM_ADDR 3'd3
`define ADMA_FDFSM_NEXT 3'd4