adma_top.v

Wishbone dma ip core

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Advanced DMA IP Core                                        ////
////                                                              ////
////  This file is part of the ADMA project                       ////
////  http://www.opencores.org/                                   ////
////                                                              ////
////  Description                                                 ////
////  ADMA IP core. Also read adma_defines.v for basic ADMA       ////
////  overview and user parameters.                               ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, [e-mail]                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adma_top.v,v $
// Revision 1.1.1.1  2002/08/13 03:12:40  lampret
// First import.
//
//
//

//`include "timescale.v"
`include "adma_defines.v"

module adma_top(
	// WISHBONE Clock and Reset
	clk_i, rst_i,

	// WISHBONE Host Interface (slave)
	h_cyc_i, h_adr_i, h_dat_i, h_sel_i, h_we_i, h_stb_i,
	h_dat_o, h_ack_o, h_err_o, h_inta_o, h_intb_o,

	// WISHBONE System Interface (master)
	s_cyc_o, s_adr_o, s_dat_o, s_sel_o, s_we_o, s_stb_o,
	s_dat_i, s_ack_i, s_err_i,

	// WISHBONE Peripheral Interface (master)
	p_cyc_o, p_adr_o, p_dat_o, p_sel_o, p_we_o, p_stb_o, p_dack_o,
	p_dat_i, p_ack_i, p_err_i, p_inta_i, p_dreq_i, p_dnd_i
);

parameter base_dma = 4'd1;
parameter dw = 32;
parameter aw = 32;
parameter lw = `ADMA_MAXLEN;

//
// WISHBONE Interface
//
input			clk_i;		// Clock
input			rst_i;		// Reset

//
// WISHBONE Host Interface (slave)
//
input			h_cyc_i;	// cycle valid input
input 	[aw-1:0]	h_adr_i;	// address bus inputs
input	[dw-1:0]	h_dat_i;	// input data bus
input	[3:0]		h_sel_i;	// byte select inputs
input			h_we_i;		// indicates write transfer
input			h_stb_i;	// strobe input
output	[dw-1:0]	h_dat_o;	// output data bus
output			h_ack_o;	// normal termination
output			h_err_o;	// termination w/ error
output			h_inta_o;	// interrupt request A
output			h_intb_o;	// interrupt request B

//
// WISHBONE System Interface (master)
//
output			s_cyc_o;	// cycle valid input
output 	[aw-1:0]	s_adr_o;	// address bus inputs
output	[dw-1:0]	s_dat_o;	// input data bus
output	[3:0]		s_sel_o;	// byte select inputs
output			s_we_o;		// indicates write transfer
output			s_stb_o;	// strobe input
input	[dw-1:0]	s_dat_i;	// output data bus
input			s_ack_i;	// normal termination
input			s_err_i;	// termination w/ error

//
// WISHBONE Peripheral Interface (master)
//
output			p_cyc_o;	// cycle valid input
output 	[aw-1:0]	p_adr_o;	// address bus inputs
output	[dw-1:0]	p_dat_o;	// input data bus
output	[3:0]		p_sel_o;	// byte select inputs
output			p_we_o;		// indicates write transfer
output			p_stb_o;	// strobe input
output			p_dack_o;	// DMA acknowledge
input	[dw-1:0]	p_dat_i;	// output data bus
input			p_ack_i;	// normal termination
input			p_err_i;	// termination w/ error
input			p_inta_i;	// interrupt request
input			p_dreq_i;	// DMA request
input			p_dnd_i;	// DMA next descriptor


`ifdef ADMA_IMPLEMENTED

//
// Length Decrement Register
//
reg	[lw:0]		ldr;	// Length decrement register

//
// Control Register Bits
//
reg	[8:0]		cr;	// Control register

//
// Descriptor Pointer Register
//
`ifdef ADMA_DESCRIPTORS
reg	[aw-1:2]	dpr;	// Descriptor pointer register
`else
wire	[aw-1:2]	dpr;	// When no real DPR
`endif

//
// Address Increment Register
//
reg	[aw-1:2]	air;	// Address increment register

//
// Internal wires & regs
//
reg			arb_prev_sys; // Previous owner of peripheral i/f
wire			arb_sel_sys; // Which i/f is connected to perip i/f
wire			sel_dma; // Select DMA registers
wire 			hwe_ldr; // Host write enable for LDR
wire			hwe_cr;	 // Host write enable for CR
wire			hwe_dpr; // Host write enable for DPR
wire			hwe_air; // Host write enable for AIR
`ifdef ADMA_DESCRIPTORS
reg 			dwe_ldr; // Descriptor write enable for LDR
reg			dwe_cr;	 // Descriptor write enable for CR
reg			dwe_dpr; // Descriptor write enable for DPR
reg			dwe_air; // Descriptor write enable for AIR
`else
wire 			dwe_ldr; // Descriptor write enable for LDR
wire			dwe_cr;	 // Descriptor write enable for CR
wire			dwe_dpr; // Descriptor write enable for DPR
wire			dwe_air; // Descriptor write enable for AIR
`endif
wire			dec_ldr; // Decrement LDR
wire			inc_air; // Increment AIR
reg	[dw-1:0]	dma_reg; // DMA register being read
`ifdef ADMA_DESCRIPTORS
reg			loading; // Loading descriptor
`else
wire			loading; // Loading descriptor
`endif
wire			inc_dpr; // Increment DPR
wire			err;	// Termination with error
reg [2:0]		fd_state;// Fetch descriptor FSM state

///////////////////////////////////////////////////////////////////////
//
// Arbiter which selects which interface connects to peripheral interface
//

//
// Store previous owner of peripheral i/f (either host or system i/f)
//
always @(posedge clk_i or posedge rst_i)
	if (rst_i)
		arb_prev_sys <= #1 1'b0;
	else if (h_ack_o | h_err_o | p_dack_o)
		arb_prev_sys <= #1 arb_sel_sys;

//
// Combinatorial logic to select current owner of peripheral interface
// based on last owner and assertion of requests from both host and
// system interface
//
assign arb_sel_sys = (arb_prev_sys & ~h_stb_i)
	| (~arb_prev_sys & s_ack_i) | (~arb_prev_sys & ~h_stb_i & ~s_ack_i);

///////////////////////////////////////////////////////////////////////
//
// Outputs of host interface
//

//
// h_err_o is valid p_err_i when host i/f is connected to perip i/f
//
assign h_err_o = p_err_i & ~arb_sel_sys;

//
// h_ack_o is valid p_ack_i when host i/f is connected to perip i/f
//
assign h_ack_o = (p_ack_i | sel_dma) & ~arb_sel_sys;

//
// h_dat_o is connected to p_dat_i or to DMA registers
//
assign h_dat_o = sel_dma ? dma_reg : p_dat_i;

//
// Host interrupt is connected directly to peripheral interrupt
//
assign h_inta_o = p_inta_i;

//
// Generate interrupt request from CR bits
//
assign h_intb_o = cr[`ADMA_CR_EN_DONEINT] & cr[`ADMA_CR_DONE]
		| cr[`ADMA_CR_EN_ERRINT] & cr[`ADMA_CR_ERR];

///////////////////////////////////////////////////////////////////////
//
// Outputs of peripheral interface
//

//
// p_dat_o is either connected to h_dat_i or s_dat_i
//
assign p_dat_o = arb_sel_sys ? s_dat_i : h_dat_i;

//
// p_cyc_o is either connected to h_cyc_i or inactive
//
assign p_cyc_o = arb_sel_sys ? 1'b0 : h_cyc_i;

//
// p_stb_o is connected to h_stb_i that does not select
// DMA registers
//
assign p_stb_o = h_stb_i & ~sel_dma;

//
// p_we_o is either connected to h_we_i or inactive
//
assign p_we_o = arb_sel_sys ? 1'b0 : h_we_i;

//
// p_sel_o is either connected to h_sel_i or 4'b1111
//
assign p_sel_o = arb_sel_sys ? 4'b1111 : h_sel_i;

//
// p_adr_o is always connected to h_adr_i
//
assign p_adr_o = h_adr_i;

//
// p_dack_o is valid s_ack_i when arb_sel_sys is asserted
//
assign p_dack_o = s_ack_i & arb_sel_sys;

///////////////////////////////////////////////////////////////////////
//
// Outputs of system interface
//

//
// We always do aligned 32-bit transfers on system interface
//
assign s_sel_o = 4'b1111;

//
// s_dat_o is always connected to p_dat_i
//
assign s_dat_o = p_dat_i;

//
// s_we_o is driven by CR[WM] when not loading descriptor
//
assign s_we_o = cr[`ADMA_CR_WM] & ~loading;

//
// s_cyc_o is asserted when CR[EN] is set or when loading descriptor
//
assign s_cyc_o = cr[`ADMA_CR_EN] | loading;