test.v

来自「verilog编写的状态机检测00100序列. 实现 input:...011」· Verilog 代码 · 共 23 行

`timescale 1ns/1ns
`include "./xcv.v"
 module xcv_Top;
reg clk,rst;
reg [23:0] data;
wire [2:0] state;
wire z,x;
assign x=data[23];
always #10 clk=~clk;
always @(posedge clk) 
        data={data[22:0],data[23]};
initial
   begin
       clk=0;
       rst=1;
       #2 rst=0;
       #30 rst=1;
       data='b0001_0010_0010_0001;
       #500 $stop;
   end
xcv m(x,z,clk,rst,state);
endmodule