_primary.vhd

verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状

library verilog;
use verilog.vl_types.all;
entity xcv is
    generic(
        IDIE            : integer := 0;
        A               : integer := 1;
        B               : integer := 2;
        C               : integer := 3;
        D               : integer := 4;
        E               : integer := 5
    );
    port(
        x               : in     vl_logic;
        z               : out    vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        state           : out    vl_logic_vector(2 downto 0)
    );
end xcv;