scan.out

来自「verilog源码」· OUT 代码 · 共 83 行

Statistics for case statements in always block at line 36 in file
        'E:/EDA/Xilinx/active/projects/version2.14/calculat/SCAN.V'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            50            |     no/auto      |
|            59            |     no/auto      |
|            68            |     no/auto      |
|            77            |     no/auto      |
|            98            |     no/auto      |
===============================================

Inferred memory devices in process 
	in routine scan line 36 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/SCAN.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       l1_reg        | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|       l2_reg        | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|       l3_reg        | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|       l4_reg        | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|      mgen_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|       mod_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|       op_reg        | Flip-flop |   1   |  -  | -  | N  | Y  | N  | N  | N  |
|       out_reg       | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|      scan_reg       | Flip-flop |   3   |  Y  | N  | Y  | N  | N  | N  | N  |
|      stop_reg       | Flip-flop |   1   |  -  | -  | N  | Y  | N  | N  | N  |
===============================================================================

l1_reg
------
    set/reset/toggle: none


l2_reg
------
    set/reset/toggle: none


l3_reg
------
    set/reset/toggle: none


l4_reg
------
    set/reset/toggle: none


mgen_reg
--------
    Async-reset: reset'


mod_reg
-------
    Async-reset: reset'


op_reg
------
    Async-set: reset'


out_reg (width 4)
-----------------
    Async-reset: reset'


scan_reg (width 3)
------------------
    Async-reset: reset'


stop_reg
--------
    Async-set: reset'


Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/scan.hnl'