freqdivide2.out

来自「verilog源码」· OUT 代码 · 共 23 行

Inferred memory devices in process 
	in routine freqdivide2 line 166 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/FREQDIVIDE.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     clkout_reg      | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|     counter_reg     | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

clkout_reg
----------
    Async-reset: reset'


counter_reg (width 2)
---------------------
    Async-reset: reset'


Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/freqdivide2.hnl'