merge.out

来自「verilog源码」· OUT 代码 · 共 35 行

Inferred memory devices in process 
	in routine merge line 53 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/MERGE.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      carry_reg      | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|    halfcarry_reg    | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|    sumlower_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
|    sumupper_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

carry_reg
---------
    set/reset/toggle: none


halfcarry_reg
-------------
    set/reset/toggle: none


sumlower_reg (width 4)
----------------------
    set/reset/toggle: none


sumupper_reg (width 4)
----------------------
    set/reset/toggle: none


Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/merge.hnl'